摘要

摘要

任意波形发生器是不断发展的数字信号处理技术和大规模集成电路工艺蕴育出来的一种新型测量仪器，能够满足人们对各种复杂信号或特殊信号的需求，代表了信号源的发展方向。可编程门阵列（FPGA）具有高集成度、高速度、可重构等特性。使用FPGA来开发数字电路，可以大大缩短设计时间，减小印制电路板的面积，提高系统的可靠性和灵活性。本课题将DDS、USB接口和虚拟仪器技术有机地结合在一起，以FPGA为硬件基础，通过系统硬件电路设计、逻辑设计和软件设计，实现了一款基于FPGA的低成本、便携式、可扩展的即插即用任意波形发生器。

本文系统的分析了DDS技术的基本组成、工作原理及其输出信号的频谱特性，给出了改善合成信号频谱纯度的方法，为任意波形发生器的设计与实现提供了理论指导。本课题从总体上规划了任意波形发生器的硬件结构，结合DDS输出信号的频谱特性，设计了两种滤波器对信号进行滤波处理，并开发了硬件平台。以Quartus II软件作为开发工具，对Cyclone II 系列FPGA芯片EP2C5Q208C8实现的DDS结构中的数字部分及该部分与USB接口进行了设计，并实现了波形的调幅、调频及多种数字调制。在此基础上，使用当前流行的虚拟仪器设计软件LabWindows/CVI，利用计算机强大的计算和显示功能，设计了任意波形发生器的操作面板。通过在操作面板上选择正弦波、方波、三角波、锯齿波、白噪声等常规波形或者手动绘制任意波形，并设置波形参数，进而控制硬件系统产生相应波形信号，充分体现了任意波形发生器的“任意性”。通过测试，证明本任意波形发生器达到了预期的设计要求。

关键词： 直接频率合成 可编程门阵列 通用串行总线 虚拟仪器

Abstract

Abstract

With the unceasing development of digital signal processing technique and VLSI technology, a new measure instrument—arbitrary waveform generator (AWG) comes into being. AWG can meet the desire of complicated and special signal, which represents the developing direction of signal sources. Field programmable gate array (FPGA) has the features of large scale integration, high working frequency and reconfiguration. It can greatly shorten design period, reduce the size of printed circuit board (PCB) and improve system reliability and flexibility to design digital circuit by use of FPGA. By combining direct frequency synthesis (DDS), universal serial bus (USB) and virtual instrument effectively, a low cost, portable and extensible AWG based on FPGA has been realized. The main contents consist of hardware design, logic design and software design are outlined as follows.

The thesis systematically introduces the composition and working principle of DDS, analyzes the spectrum characteristics of its output, and gives the methods of reducing the noise, which presents the theoretical guidance for design and realization of AWG. The structure of AWG is planned from the overall and the circuit is presented. Considering the spectrum characteristics of DDS’s output, two kinds of filters are designed to filter signals unwanted. The digital part in DDS and its interface with USB are designed on the Cyclone II FPGA chip EP2C5Q208C8 with Quartus II. This digital part can realize amplitude modulation (AM), frequency modulation (FM) and several kinds of digital modulation. On this basis, taking advantage of PC’s powerful calculation and displaying capability, we design the operation panel of AWG with LabWindows/CVI. On the panel user can choose conventional waves such as sine wave, square wave, triangle wave, sawtooth wave, white noise ect., or draw waves by hand, and set wave parameters to control instrunment generate corresponding waveform, which embodies the “arbitrary” character of AWG.. The result of experimentation proves that this AWG has attained the desire of design.

Keywords： DDS FPGA USB Virtual Instrument

目录

目录

第一章 绪论 .......................................................... 1

1.1 引言 ..................................................................................................................... 1

1.2 任意波形发生器的功能 ..................................................................................... 2 1.3 国内外发展现状 ................................................................................................. 3 1.4 课题研究目标 ..................................................................................................... 4 1.5 主要研究工作及论文内容安排 ......................................................................... 5 第二章 任意波形发生器的理论分析 ...................................... 7

2.1 频率合成技术及性能指标 ................................................................................. 7

2.2 DDS原理分析 ................................................................................................... 10

2.2.1 DDS基本结构 ......................................................................................... 11 2.2.2 DDS原理 ................................................................................................. 12 2.2.3 DDS技术特点 ......................................................................................... 16 2.3 DDS输出特性 ................................................................................................... 18

2.3.1 理想情况下DDS的频谱特性 ............................................................... 18 2.3.2 非理想情况下DDS的频谱特性 ........................................................... 20 2.4 DDS杂散抑制方法 ........................................................................................... 25 第三章 任意波形发生器的硬件电路设计 ................................. 29

3.1 系统设计方案 ................................................................................................... 29

3.2 系统总体结构 ................................................................................................... 29 3.3 功能模块设计 ................................................................................................... 30

3.3.1 FPGA电路 .............................................................................................. 30 3.3.2 D/A转换电路 .......................................................................................... 33 3.3.3 滤波器的设计 ......................................................................................... 35 3.3.4 放大衰减及直流偏置电路 ..................................................................... 39 3.3.5 外部接口电路 ......................................................................................... 42 3.3.6 电源电路 ................................................................................................. 45 3.4 印制电路板的设计 ........................................................................................... 45 第四章 FPGA逻辑设计 ................................................ 47

4.1 FPGA及其开发环境简介 ................................................................................ 47

4.1.1 现场可编程门阵列简介 ......................................................................... 47 4.1.2 Quartus II 7.1集成开发环境 .................................................................. 48 4.2 任意波形发生器的FPGA实现 ...................................................................... 49

4.2.1 地址译码和控制数据寄存模块 ............................................................. 50 4.2.2 移位寄存器控制逻辑 ............................................................................. 51 4.2.3 数字电位器控制逻辑 ............................................................................. 52 4.2.4 相位累加器的设计 ................................................................................. 53