.layer0_top(12'd0), .layer0_left(12'd0), .layer0_width(12'd1024), .layer0_height(12'd768), .layer0_alpha(8'hff),

.layer0_rdreq(ch1_vout_rd_req), .layer0_ycbcr(ch1_vout_ycbcr) );

mem_ctrl #(

.MEM_DATA_BITS(MEM_DATA_BITS) )

mem_ctrl_m0(

.rst_n(rst_n), .source_clk(clk), .phy_clk(phy_clk), .aux_half_rate_clk(),

.ch0_rd_burst_req(ch0_rd_burst_req), .ch0_rd_burst_len(ch0_rd_burst_len), .ch0_rd_burst_addr(ch0_rd_burst_addr),

.ch0_rd_burst_data_valid(ch0_rd_burst_data_valid), .ch0_rd_burst_data(ch0_rd_burst_data), .ch0_rd_burst_finish(ch0_rd_burst_finish),

.ch1_rd_burst_req(ch1_rd_burst_req), .ch1_rd_burst_len(ch1_rd_burst_len), .ch1_rd_burst_addr(ch1_rd_burst_addr),

.ch1_rd_burst_data_valid(ch1_rd_burst_data_valid), .ch1_rd_burst_data(ch1_rd_burst_data), .ch1_rd_burst_finish(ch1_rd_burst_finish),

.ch2_rd_burst_req(ch2_rd_burst_req), .ch2_rd_burst_len(ch2_rd_burst_len), .ch2_rd_burst_addr(ch2_rd_burst_addr),

.ch2_rd_burst_data_valid(ch2_rd_burst_data_valid), .ch2_rd_burst_data(ch2_rd_burst_data), .ch2_rd_burst_finish(ch2_rd_burst_finish),

.ch3_rd_burst_req(ch3_rd_burst_req), .ch3_rd_burst_len(ch3_rd_burst_len), .ch3_rd_burst_addr(ch3_rd_burst_addr),

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.ch3_rd_burst_data_valid(ch3_rd_burst_data_valid), .ch3_rd_burst_data(ch3_rd_burst_data), .ch3_rd_burst_finish(ch3_rd_burst_finish),

/////////////////////////////////////////// .ch0_wr_burst_req(ch0_wr_burst_req), .ch0_wr_burst_len(ch0_wr_burst_len), .ch0_wr_burst_addr(ch0_wr_burst_addr),

.ch0_wr_burst_data_req(ch0_wr_burst_data_req), .ch0_wr_burst_data(ch0_wr_burst_data), .ch0_wr_burst_finish(ch0_wr_burst_finish),

.ch1_wr_burst_req(ch1_wr_burst_req), .ch1_wr_burst_len(ch1_wr_burst_len), .ch1_wr_burst_addr(ch1_wr_burst_addr),

.ch1_wr_burst_data_req(ch1_wr_burst_data_req), .ch1_wr_burst_data(ch1_wr_burst_data), .ch1_wr_burst_finish(ch1_wr_burst_finish),

.ch2_wr_burst_req(ch2_wr_burst_req), .ch2_wr_burst_len(ch2_wr_burst_len), .ch2_wr_burst_addr(ch2_wr_burst_addr),

.ch2_wr_burst_data_req(ch2_wr_burst_data_req), .ch2_wr_burst_data(ch2_wr_burst_data), .ch2_wr_burst_finish(ch2_wr_burst_finish),

.ch3_wr_burst_req(ch3_wr_burst_req), .ch3_wr_burst_len(ch3_wr_burst_len), .ch3_wr_burst_addr(ch3_wr_burst_addr),

.ch3_wr_burst_data_req(ch3_wr_burst_data_req), .ch3_wr_burst_data(ch3_wr_burst_data), .ch3_wr_burst_finish(ch3_wr_burst_finish),

///////////////////////////////////// .mem_cs_n(mem_cs_n), .mem_cke(mem_cke), .mem_addr(mem_addr), .mem_ba(mem_ba),

.mem_ras_n(mem_ras_n), .mem_cas_n(mem_cas_n), .mem_we_n(mem_we_n), .mem_clk(mem_clk), .mem_clk_n(mem_clk_n),

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.mem_dm(mem_dm), .mem_dq(mem_dq), .mem_dqs(mem_dqs), .mem_odt(mem_odt) );

endmodule

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