改进版-Soc Encounter数字版图V1.4 下载本文

基于hejian18及SMIC18及charter.35工艺的SOC Ecounter数字版

图设计流程

V1.4

Updated: 2009-2-24

V1.0 V1.1 V1.2 Initial version 修改部分错误 1. 修改部分错误 2. 增加SMIC18_EE_2P4M工艺 SMIC与hejian相异处,注以说明 增加附1-PAD的说明 增加charter0.35um无PAD工艺设计流程 朱秋玲 2008.5.7 张春 臧仕平2009.2.20 V1.3 V1.4 张春2009.2.21 王志军2009.2.24 1

目录

1 文件准备(异) ................................................................................................................................ 4 1.1 库文件的准备 ............................................................................................................................. 4

1.2 根据设计自己准备的文件 ........................................................................................................ 5

2 运行软件...................................................................................................................................... 8 3 Design_import(异) ................................................................................................................ 9 4

Load DEF文件和IO file 文件 .................................................................................................. 12

5 Global Net Connection ........................................................................................................... 13 6 FloorPlan .................................................................................................................................... 14 7 Add Power Rings ...................................................................................................................... 16 8 Add Stripes (可选) ............................................................................................................. 17 9 Placement Blockage (可选) ............................................................................................... 18 10 Placement ................................................................................................................................ 19 11 Special Route (SRoute) ....................................................................................................... 20 12 Creat clock tree spec ......................................................................................................... 21 14 Post–CTS Optimization ....................................................................................................... 24 15 Trail Routing ........................................................................................................................ 25 16 Nano Routing .......................................................................................................................... 26 17 IO Filling .............................................................................................................................. 27 18 Add Filling ............................................................................................................................ 28 19 Post–Route Optimization ................................................................................................... 29 20 生成SDF时序文件 .................................................................................................................. 30 21 Verify connectivity............................................................................................................. 31 22 Verify Geometry .................................................................................................................... 32 23 Export Files(异) .............................................................................................................. 33

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24 版图验证——导入ICFB(异) .............................................................................................. 38 1 HEJIAN18 .................................................................................................................................... 38 2 SMIC18 ....................................................................................................................................... 40 3 charter0.35 ................................................................................................................................. 40 25 DRC(异) ................................................................................................................................... 41 1 HEJIAN18 ...................................................................................................................................... 41

2 SMIC18 .......................................................................................................................................... 42 3 charter0.35 ................................................................................................................................ 42 26 LVS ........................................................................................................................................... 43 1 HEJIAN18 ...................................................................................................................................... 43

2 SMIC .............................................................................................................................................. 45

3 charter0.35 ................................................................................................................................... 45 27 后仿真 ..................................................................................................................................... 47 28 版图体会 .................................................................................................................................. 48 附一 关于umc18工艺库IO PAD的使用 ..................................................................................... 49 附二 charter0.35进行图层转换(24步:版图验证—导入ICFB)时的Hercules文件及map文件 ........................................................................................................................................................ 50

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1 文件准备(异)

1.1 库文件的准备

对于 SOC Encounter而言后端设计所需的数据主要有是Foundry厂提供的标准单元和I/O Pad的库文件,它包括物理库、时序库,分别以.lef、.tlf(或者.lib,更好)的形式给出,其中I/O Pad 的相关库文件只有在做有Pad的版图时才需要,否则不需要。对于hejian18的工艺,版图设计所需要的库文件及其在ICAS组各个服务器上的目录路径分别如下:

Hejian18:

1 Lef文件:

/library/hjtc18_artisan_fb/SC/aci/sc-x/lef/hejian18_6lm.lef (标准单元)/library/hjtc18_artisan_fb/IO/aci/io/lef/arti_HEJ018_io3v5v_6lm.lef(IO库)

2 时序库文件(timing libraries) Max timing libraries:

/library/hjtc18_artisan_fb/SC/aci/sc-x/synopsys/slow.lib /library/hjtc18_artisan_fb/IO/aci/io/synopsys/arti_HEJ018io_syn_ss_1p 62_3p0_125C.lib

Min timing libraries:

/library/hjtc18_artisan_fb/SC/aci/sc-x/synopsys/fast.lib /library/hjtc18_artisan_fb/IO/aci/io/synopsys/arti_HEJ018io_syn_ff_1p98_3p6_0C.lib

SMIC18 2p4m:

1 Lef文件:

/data3/library/smic18_artisan_fb/aci/sc-x/lef/smic18_4lm.lef (标准单元) 如果不是4层金属,注意选择的文件不相同。

2 时序库文件(timing libraries) Max timing libraries:

/data3/library/smic18_artisan_fb/aci/sc-x/synopsys/slow.lib Min timing libraries:

/data3/library/smic18_artisan_fb/aci/sc-x/synopsys/fast.lib

Charter0.35um EEPROM:

1 Lef文件:

cb35_stk_3lm.lef(通孔大小,金属线线宽等信息)cb35os142.lef(标准单元的布局布线信息)

2 时序库文件(timing libraries) Max timing libraries:cb35os142_max.lib Min timing libraries:cb35os142_min.lib

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说明:

(1) 这里的时序库文件用的是.lib文件,如果没有.lib文件,用.tlf文件也可以,建议

用.lib文件,信息比较全。Charter0.35um工艺的tlf文件要求4.3版本以上才行,现有的tlf文件无法使用。

(2) 库的网表库(verilog文件)这里不需要。只在后仿真的时候需要。 (3) SMIC:服务器没有相关的io文件,故没有做加PAD的流程。

1.2 根据设计自己准备的文件

需要自己准备的和设计相关的文件是verilog网单, sdc时序文件,def电源pad声明文件,io位置说明文件。

(1)DC综合后的网单文件(.v格式)。对于有PAD的情况,还需要在网单里面加入输入输出的IO PAD,具体可查阅库中doc目录下的相关pdf文件,选择合适的输入输出pad。这里用的是hejian工艺的P8A的IO PAD,顶层网单修改如下(原设计 顶层module名是ram_top):

module tag_with_pads ( rst, clk, pie_data_in, ss_out, err); input rst, clk, pie_data_in; output ss_out, err;

wire w_rst, w_clk, w_pie_data_in, w_ss_out, w_err;//link to core

ram_top u_ram_top (.rst(w_rst), .clk(w_clk), .pie_data_in(w_pie_data_in), .ss_out(w_ss_out),.err(w_err)); P8A pad_rst

( .P(rst), .Y(w_rst), .A(1'b0), .ODEN(1'b0), .OCEN(1'b0), .PU(1'b1), .PD(1'b0), .CEN(1'b1), .CSEN(1'b0) ); P8A pad_clk ( .P(clk) , .Y(w_clk), .A(1'b0), .ODEN(1'b0), .OCEN(1'b0), .PU(1'b1), .PD(1'b0), .CEN(1'b1), .CSEN(1'b0) ); P8A pad_pie_data_in ( .P(pie_data_in), .Y(w_pie_data_in), .A(1'b0), .ODEN(1'b0), .OCEN(1'b0), .PU(1'b1), .PD(1'b0), .CEN(1'b1), .CSEN(1'b0) ); P8A pad_ss_out ( .P(ss_out), .A(w_ss_out), .ODEN(1'b1), .OCEN(1'b1), .PU(1'b1), .PD(1'b0), .CEN(1'b1), .CSEN(1'b0) ); P8A pad_err

( .P(err), .A(w_err), .ODEN(1'b1), .OCEN(1'b1), .PU(1'b1), .PD(1'b0), .CEN(1'b1), .CSEN(1'b0) ); endmodule

补充说明:

(1)PAD可以在综合前加入也可以在综合后加入,如果在综合前加入,综合工具可以优化驱动和负载,需要在综合的tcl文件里把时钟信号和Pad设置成为不被综合,因为时钟树在下

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