实验二 常用指令实验 1 exp01.asm
;the program is compiled at no autoinitialization mode
.mmregs .global _main
#3000h,sp
_main: stm
ssbx xf
call delay rsbx xf
call delay b _main nop
nop
;delay .5 second delay:
stm 270fh,ar3
loop1: stm 0f9h,ar4 loop2: banz loop2,*ar4- banz loop1,*ar3-
ret nop
nop ;stm 2 cycles ;banz when TRUE 4 cycles ; FALSE 2 cycles ;0f9h=>249d ;270fh=>9999d .end
2.exp01.cmd
MEMORY {
PAGE 0: /* program space */
VECS: origin = 0x0080, length = 0x0080 /* 128bytes vector table space */ PROG: origin = 0x0100, length = 0x2F00 /* 8K program memory space */ PAGE 1: /* data space */
SCRA: origin = 0x0060, length = 0x0020 /* scratch pad mem space */
STCK: origin = 0x2000, length = 0x0800 /* 1K words for stack */ DAT1: origin = 0x2800, length = 0x0100 /* 256 words for sys data */ DAT2: origin = 0x2900, length = 0x1000 /* 12K words for appl data */ }
SECTIONS
{
.vectors : {} > VECS PAGE 0 /* interrupt vector table */ .text : {} > PROG PAGE 0 /* program code */
.data : {} > DAT2 PAGE 1 /* initialized data */
.coeffs : {} > PROG PAGE 0 /* initialized parameters */
.stack : {} > STCK PAGE 1 /* software stack section */ .variable : {} > DAT1 PAGE 1 /* uninitialized vars for DSP&AIC10 */ .bss : {} > DAT2 PAGE 1 /* uninitialized vars for applications */ }
实验三 数据存储实验 1.exp02.asm
;get some knowledge of the cmd file
;the program is compiled at no autoinitialization mode .mmregs .global _main _main:
;store data ;
stm 1000h,ar1 ;address of internal memory
stm 5000h,ar1 ;address of exterior memory rpt #07h st 0aaaah,*ar1+ ;data
;read data then re-store stm 7h,ar3 ; ;
stm 5000h,ar1 ;address of exterior memory stm 5008h,ar2 ;address of exterior memory stm
1000h,ar1
stm 1008h,ar2 loop:
ld st
*ar1+,t t,*ar2+
banz loop,*ar3- here:
b here
.end
2.exp02.cmd
MEMORY {
PAGE 0: PROG: origin = 0x80, len = 0x980 /* PAGE 0: PROG: origin =0x180, using this line,then watch the result*/ }
SECTIONS {
.text: {} > PROG PAGE 0 .cinit: {} > PROG PAGE 0 .switch: {} > PROG PAGE 0 .bss: {} > DATA PAGE 1 .const: {} > DATA PAGE 1 .sysmem: {} > DATA PAGE 1 .stack: {} > DATA PAGE 1 .data: {} > DATA PAGE 1 }
len=0x980(you can repace the line above by
PAGE 1: DATA: origin = 0x0a00, len = 0x0a00
实验四 语音处理实验 1. InitC5402.asm
.global _InitC5402 .global _OpenMcBSP .global _CloseMcBSP
.global _READAD50 .global _WRITEAD50
.include MMRegs.h _InitC5402:
NOP
LD #0, DP ; reset data–page pointer
STM #0, CLKMD ; software setting of DSP clock STM #0, CLKMD ; (to divider mode before setting)
STM #0x4007, CLKMD ; set C5402 DSP clock to 40MHz
* STM #0x4007, CLKMD ; set C5402 DSP clock to 100MHz ; (based on DSK crystal at 20MHz)
******* Configure C5402 System Registers ******* STM #0x2000, SWWSR ; 2 wait cycle for IO space & ; 0 wait cycle for data&prog spaces
STM #0x0000,BSCR ; set wait states for bank switch:
; 64k mem bank, extra 0 cycle between ; consecutive prog/data read
; STM #0x1800,ST0 ; ST0 at default setting
; STM #0x2900,ST1 ; ST1 at default setting(note:INTX=1) ;
STM #0x00A0,PMST ; MC mode & OVLY=1, vectors at 0080h STM #0x0010, TCR ; stop on–chip timer0 STM #0x0010, TCR1 ; stop on–chip timer1 ******* Set up Timer Control Registers *******
; Timer0 is used as main loop timer
; STM #2499, PRD ; timer0 rate=CPUCLK/1/(PRD+1) ; =40M/2500=16KHz
* STM #6249, PRD ; if CPU at 100M/6250=16KHz
******* Initialize McBSP1 Registers ******* STM SPCR1, McBSP1_SPSA ; register subaddr of SPCR1 STM #0000h, McBSP1_SPSD ; McBSP1 recv = left–justify ; RINT generated by frame sync
STM SPCR2, McBSP1_SPSA ; register subaddr for SPCR2 ; XINT generated by frame sync STM #0000h, McBSP1_SPSD ; McBSP1 Tx = FREE(clock stops ; to run after SW breakpoint STM RCR1, McBSP1_SPSA ; register subaddr of RCR1
STM #0040h, McBSP1_SPSD ; recv frame1 Dlength = 16 bits STM RCR2, McBSP1_SPSA ; register subaddr of RCR2
STM #0040h, McBSP1_SPSD ; recv Phase = 1 ; ret frame2 Dlength = 16bits STM XCR1, McBSP1_SPSA ; register subaddr of XCR1
STM #0040h, McBSP1_SPSD ; set the same as recv STM XCR2, McBSP1_SPSA ; register subaddr of XCR2 STM #0040h, McBSP1_SPSD ; set the same as recv STM PCR, McBSP1_SPSA ; register subaddress of PCR
STM #000eh, McBSP1_SPSD ; clk and frame from external (slave) ; FS at pulse–mode(00)
******* Finish DSP Initialization *******
STM #0x0000, IMR ; disable peripheral interrupts STM #0xFFFF, IFR ; clear the intrupts’ flags RET ; return to main NOP
NOP
******* Waiting for McBSP0 RX Finished *******
IfRxRDY1:
NOP
STM SPCR1, McBSP1_SPSA ; enable McBSP1 Rx LDM McBSP1_SPSD, A
AND #0002h, A ; mask RRDY bit BC IfRxRDY1, AEQ ; keep checking NOP NOP
RET ; return NOP
NOP
******* Waiting for McBSP0 TX Finished ******* IfTxRDY1: NOP
STM SPCR2, McBSP1_SPSA ; enable McBSP1 Tx LDM McBSP1_SPSD, A
AND #0002h, A ; mask TRDY bit BC IfTxRDY1, AEQ ; keep checking NOP NOP RET ; return
NOP NOP
****************************************** ****************************************** _OpenMcBSP:
rsbx xf call wait NOP
STM SPCR1, McBSP1_SPSA ; enable McBSP0 RX for ADC data in LDM McBSP1_SPSD,A OR #0x0001, A
STLM A, McBSP1_SPSD
STM SPCR2, McBSP1_SPSA ; enable McBSP0 TX for DTMF out LDM McBSP1_SPSD,A OR #0x0001, A
STLM A, McBSP1_SPSD LD #0h, DP ; load data page 0 rpt #23 NOP