8-7 将例8-11(欲设计4选1三态总线)中的四个IF语句分别用四个并列进程语句表达出来。
--8-7 修改【例8-11】(欲设计4选1三态总线)，用4个进程设计4选1通道三态总线(8位)电路 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY tristate2 IS
port(input3,input2,input1,input0 :
IN STD_LOGIC_VECTOR(7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY tristate2 ;
ARCHITECTURE multiple_drivers OF tristate2 IS BEGIN
COM3: PROCESS(enable,input3) BEGIN
IF enable=\ END PROCESS;
COM2: PROCESS(enable,input2) BEGIN
IF enable=\ END PROCESS;
COM1: PROCESS(enable,input1) BEGIN
IF enable=\ END PROCESS;
COM0: PROCESS(enable,input0) BEGIN
IF enable=\ END PROCESS;
END ARCHITECTURE multiple_drivers;
10 习 题
10-1 举二例说明，有哪些常用时序电路是状态机比较典型的特殊形式，并说明它们属于什么类型的状态机(编码类型、时序类型和结构类型)。（提示：二进制计数器、“00000001”左循环移位寄存器）
解：1）二进制计数器、循环移位寄存器。
2）二进制计数器：Moore型状态机；顺序编码；状态编码直接输出。 3）“00000001”左循环移位寄存器：Moore型状态机；一位热码；状态编码直接输出。
--(1)计数器：Moore型状态机；顺序编码；状态编码直接输出。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT IS
PORT(CLK: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT: OUT STD_LOGIC); END COUNT;
ARCHITECTURE behav OF COUNT IS
type STATE is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15); type arr_STATE is array(STATE) of STD_LOGIC_VECTOR(3 DOWNTO 0);
constant val_arr_STATE: arr_STATE:=(\ \
SIGNAL cs: STATE; BEGIN
PROCESS(cs)
BEGIN --时序组合主控进程，次态转换 IF CLK'EVENT AND CLK='1' THEN CASE cs IS
WHEN s0 => cs<=s1; WHEN s1 => cs<=s2; WHEN s2 => cs<=s3; WHEN s3 => cs<=s4; WHEN s4 => cs<=s5; WHEN s5 => cs<=s6; WHEN s6 => cs<=s7; WHEN s7 => cs<=s8; WHEN s8 => cs<=s9; WHEN s9 => cs<=s10; WHEN s10=> cs<=s11; WHEN s11=> cs<=s12; WHEN s12=> cs<=s13; WHEN s13=> cs<=s14; WHEN s14=> cs<=s15; WHEN s15=> cs<=s0; WHEN OTHERS=> cs<=s0; END CASE; END IF;
IF cs=s15 then COUT<='1'; else COUT<='0'; END IF; END PROCESS;
Q<=val_arr_STATE(cs); END behav;
--(2)\左循环移位寄存器：Moore型状态机；一位热码；状态编码直接输出。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY LEFT_SHIFT IS
PORT(CLK: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); Cy: OUT STD_LOGIC); END LEFT_SHIFT;
ARCHITECTURE behav OF LEFT_SHIFT IS
type STATE is(s0,s1,s2,s3,s4,s5,s6,s7);
type arr_STATE is array(STATE) of STD_LOGIC_VECTOR(7 DOWNTO 0);
constant val_arr_STATE: arr_STATE:=(\ \
SIGNAL cs: STATE; BEGIN
PROCESS(cs)
BEGIN --时序组合主控进程，次态转换 IF CLK'EVENT AND CLK='1' THEN CASE cs IS
WHEN s0 => cs<=s1; WHEN s1 => cs<=s2; WHEN s2 => cs<=s3; WHEN s3 => cs<=s4; WHEN s4 => cs<=s5; WHEN s5 => cs<=s6; WHEN s6 => cs<=s7; WHEN s7 => cs<=s0; WHEN OTHERS=> cs<=s0; END CASE; END IF; END PROCESS;
Q<=val_arr_STATE(cs); Cy<=val_arr_STATE(cs)(7); END behav;
10-2 修改例10-1，将其主控组合进程分解为两个进程，一个负责状态转换，另一个负责输出控制信号。
--10-2 修改例10-1，将其主控组合进程分解为两个进程，一个负责状态转换，另一个负责输出控制信号。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY s_machine IS
PORT(clk,reset : IN STD_LOGIC;--主控时序进程时钟驱动和复位信号
state_inputs : IN STD_LOGIC_VECTOR (0 TO 1);--外部输入信号 comb_outputs :OUT INTEGER RANGE 0 TO 15 ); --对外输出信号 END s_machine;
ARCHITECTURE behv OF s_machine IS
TYPE FSM_ST IS (s0, s1, s2, s3); --数据类型定义，状态符号化 SIGNAL c_st, next_state: FSM_ST;--将现态和次态定义为新的数据类型 BEGIN
REG: PROCESS (reset,clk) BEGIN
IF reset ='0' THEN c_st <= s0;--检测异步复位信号 ELSIF clk='1' AND clk'EVENT THEN c_st <= next_state; END IF; END PROCESS;
COM1: PROCESS(c_st, state_Inputs)--主控组合进程(现态和外部输入为敏感信号) BEGIN
CASE c_st IS
WHEN s0 => IF state_inputs = \输入为“00”，在s0踏步 ELSE next_state<=s1;END IF;--否则进入s1 WHEN s1 => IF state_inputs = \输入为“00”，在s1踏步 ELSE next_state<=s2;END IF; --否则进入s2 WHEN s2 => IF state_inputs = \输入为“11”，进入s0 ELSE next_state<=s3;END IF; --否则进入s3 WHEN s3 => IF state_inputs = \输入为“11”，在s3踏步 ELSE next_state<=s0;END IF; --否则返回s0 END case; END PROCESS;
COM2: PROCESS(c_st, state_Inputs)--主控组合进程(现态和外部输入为敏感信号) BEGIN
CASE c_st IS
WHEN s0 => comb_outputs<= 5; --现态为s0时，对外输出命令信号5编码 WHEN s1 => comb_outputs<= 8; --现态为s1时，对外输出命令信号8编码 WHEN s2 => comb_outputs<= 12; --现态为s2时，对外输出命令信号12编码 WHEN s3 => comb_outputs<= 14; --现态为s3时，对外输出命令信号14编码 END case; END PROCESS; END behv;
10-3 改写例10-1，用宏定义语句定义状态变量，给出仿真波形(含状态变量)，与图10-3作比较。注意设置适当的状态机约束条件。
--10-3 改写例10-1，用宏定义语句定义状态变量，给出仿真波形(含状态变量)，与图10-3作比较。注意设置适当的状态机约束条件。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY s_machine IS
PORT(clk,reset : IN STD_LOGIC;--主控时序进程时钟驱动和复位信号 state_inputs : IN STD_LOGIC_VECTOR (0 TO 1);--外部输入信号 comb_outputs :OUT INTEGER RANGE 0 TO 15 ); --对外输出信号 END s_machine;
ARCHITECTURE behv OF s_machine IS
-- TYPE FSM_ST IS (s0, s1, s2, s3); --数据类型定义，状态符号化 -- attribute syn_encoding
: string;
-- attribute syn_encoding of FSM_ST : type is \
SIGNAL c_st, next_state: STD_LOGIC_VECTOR(1 DOWNTO 0);--FSM_ST;--将现态和次态定义为新的数据类型
CONSTANT s0: STD_LOGIC_VECTOR(1 DOWNTO 0):=\状态符号编码定义 CONSTANT s1: STD_LOGIC_VECTOR(1 DOWNTO 0):=\ CONSTANT s2: STD_LOGIC_VECTOR(1 DOWNTO 0):=\ CONSTANT s3: STD_LOGIC_VECTOR(1 DOWNTO 0):=\BEGIN
REG: PROCESS (reset,clk) BEGIN
IF reset ='0' THEN c_st <= s0;--检测异步复位信号 ELSIF clk='1' AND clk'EVENT THEN c_st <= next_state; END IF; END PROCESS;
COM:PROCESS(c_st, state_Inputs)--主控组合进程(现态和外部输入为敏感信号) BEGIN
CASE c_st IS
WHEN s0 => comb_outputs<= 5; --现态为s0时，对外输出命令信号5编码 IF state_inputs = \输入为“00”，在s0踏步 ELSE next_state<=s1;END IF; --否则进入s1 WHEN s1 => comb_outputs<= 8; --现态为s1时，对外输出命令信号8编码 IF state_inputs = \输入为“00”，在s1踏步 ELSE next_state<=s2;END IF; --否则进入s2 WHEN s2 => comb_outputs<= 12; --现态为s2时，对外输出命令信号12编码 IF state_inputs = \输入为“11”，进入s0 ELSE next_state<=s3;END IF; --否则进入s3 WHEN s3 => comb_outputs<= 14; --现态为s3时，对外输出命令信号14编码 IF state_inputs = \输入为“11”，在s3踏步 ELSE next_state<=s0;END IF; --否则返回s0 END case; END PROCESS; END behv;
10-4 为例10-2的LOCK信号增加keep属性，再给出此设计的仿真波形(注意删去LOCK_T)。
--10-4 为例10-2(Moore型ADC0809采样)的LOCK信号增加keep属性。