WHEN st3=> IF DIN1='1' THEN PST<=st4; ELSE PST<=st3; END IF; IF DIN2='0' THEN Q<=\ WHEN st4=> IF DIN1='0' THEN PST<=st0; ELSE PST<=st4; END IF; IF DIN2='1' THEN Q<=\ WHEN OTHERS=> PST<=st0;Q<=\ END CASE; END IF;

END PROCESS REGCOM; END behav;

--(3)以例10-6为例参照表10-3的约翰逊编码单进程MEALY状态机。 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY MEALY2 IS

PORT(CLK,DIN1,DIN2,RST: IN STD_LOGIC;--时钟/串行数据/复位 Q: OUT STD_LOGIC_VECTOR(4 DOWNTO 0));--检测结果输出 END MEALY2;

ARCHITECTURE behav OF MEALY2 IS

TYPE states IS (st0,st1,st2,st3,st4);--定义各状态 attribute syn_encoding : string;

attribute syn_encoding of states : type is \ SIGNAL PST : states;

BEGIN PROCESS(CLK,RST,PST,DIN1,DIN2) BEGIN --决定转换状态的进程 IF RST='1' THEN PST <= ST0;--复位 ELSIF CLK'EVENT AND CLK='1' THEN CASE PST IS --DIN1影响状态切换

WHEN st0=> IF DIN1='1' THEN PST<=st1; ELSE PST<=st0; END IF; IF DIN2='1' THEN Q<=\ WHEN st1=> IF DIN1='1' THEN PST<=st2; ELSE PST<=st1; END IF; IF DIN2='0' THEN Q<=\ WHEN st2=> IF DIN1='1' THEN PST<=st3; ELSE PST<=st2; END IF; IF DIN2='1' THEN Q<=\ WHEN st3=> IF DIN1='1' THEN PST<=st4; ELSE PST<=st3; END IF; IF DIN2='0' THEN Q<=\ WHEN st4=> IF DIN1='0' THEN PST<=st0; ELSE PST<=st4; END IF; IF DIN2='1' THEN Q<=\ WHEN OTHERS=> PST<=st0;Q<=\ END CASE; END IF;

END PROCESS REGCOM; END behav;