《数字系统设计》总复习题 下载本文

When others => n_st <= st0; End case; End process; End one;

(三十七)在下面横线上填上合适的语句,完成下参数可定制带计数使能异步复位计数器的VHDL设计。

-- N-bit Up Counter with Load, Count Enable, and -- Asynchronous Reset library ieee;

use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all;

entity counter_n is

(width : integer := 8);

port(data : in std_logic_vector (width-1downto 0); load, en, clk, rst : in std_logic;

q : out std_logic_vector ( downto 0)); end counter_n;

architecture behave of counter_n is

signal count : std_logic_vector (width-1 downto 0); begin

process(clk, rst) begin

if rst = '1' then

count <= ; ―― 清零

elsif clk’event and clk = ‘1’ then ―― 边沿检测 if load = '1' then count <= data;

en = '1' then count <= count + 1; end ; end if; end process; q <= count; end behave;

(三十八)在下面横线上填上合适的语句,完成下图所示RTL原理图的VHDL设计。

IBARRY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MYCIR IS

PORT ( XIN, CLK : IN STD_LOGIC; YOUT : OUT STD_LOGIC); END MYCIR;

ARCHITECTURE ONE OF MYCIR IS SIGNAL A, B, C; BEGIN

B <= XIN OR ; PROCESS (CLK) BEGIN

IF CLK’EVENT AND CLK = ‘1’ THEN A <= ; C <= ; END IF; END PROCESS; YOUT <= C; END ONE;

(三十九)在下面横线上填上合适的语句,完成下图所示RTL原理图的VHDL设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY MYCIR IS

PORT (A, CLK : IN STD_LOGIC; C, B : OUT STD_LOGIC ); END MYCIR;

ARCHITECTURE BEHAV OF MYCIR IS SIGNAL TA : STD_LOGIC; BEGIN

PROCESS (A, CLK) BEGIN

IF CLK’EVENT AND CLK = ‘1’ THEN TA <= A;

B <= ; C <= ; END IF; END PROCESS; END BEHAV;

(四十)在下面横线上填上合适的语句,完成下图所示RTL原理图的VHDL设计。

Library ieee;

Use ieee.std_logic_1164.all;

Entity mycir is

Port (ain , bin , clk : in std_logic; Cout : out std_logic); End mycir;

Architecture one of mycir is Signal tb, tc; Begin

Process (clk) begin

If clk’event and clk = ‘1’ then tb <= bin; end if; End process;

Process (clk, tc) begin

If clk = ‘1’ then cout <= ; end if;

End process;

Tc <= ain xor ; End one;

(四十一)在下面横线上填上合适的语句,完成简易彩灯控制电路的VHDL设计。

说明: 该控制电路控制红、绿、黄三个发光管循环发亮。要求红发光管亮2秒,绿发光管亮3秒,黄发光管亮1秒。 LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY asm_led IS

PORT(clr,clk:IN std_logic; led1,led2,led3:OUT std_logic); END;

ARCHITECTURE a OF asm_led IS

states IS (s0,s1,s2,s3,s4,s5); SIGNAL q: std_logic_vector(0 TO 2); SIGNAL state:states; BEGIN

p1:PROCESS(clk, ) BEGIN

IF(clr=’0’) THEN state<=s0;

ELSIF(clk’ebent AND clk=’1’) THEN CASE state IS

WHEN s0=>state<=s1; WHEN s1=>state<=s2; WHEN s2=>state<=s3; When s3=>state<=s4; WHEN s4=>state<=s5; WHEN s5=>state<=s0;

END CASE; END IF;

END PROCESS p1;

p2:PROCESS(clr, ) BEGIN

IF clr=’0’ THEN led1<=’1’;led2<=’0’;led3<=’0’; ELSE CASE state IS

WHEN s0=> led1<=’1’;led2<=’0’;led3<=’0’; WHEN s1=> led1<=’0’;led2<=’1’;led3<=’0’; WHEN s2=> led1<=’0’;led2<=’1’;led3<=’0’; WHEN s3=> led1<=’0’;led2<=’0’;led3<=’1’; WHEN s4=> led1<=’0’;led2<=’0’;led3<=’1’; WHEN s5=> led1<=’0’;led2<=’0’;led3<=’1’; END CASE; END IF;

END PROCESS p2; END ARCHITECTURE a;

(四十一)在下面横线上填上合适的语句,完成简易彩灯控制电路的VHDL设计。

说明:在eda实验箱上利用OUT1~OUT8共8个发光二极管实现从左到右再从右到左循环,依次仅有一只led不亮的简单跑马灯。

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; USE ieee.std_logic_arith.ALL; ENTITY test2 IS

PORT (clk1hz:IN std_logic;

led:OUT std_logic_vector(7 DOWNTO 0)); END test2;

ARCHITECTURE beha OF test2 IS

SIGNAL count1:std_logic_vector (3 DOWNTO 0); BEGIN

p1:PROCESS (clk1hz) BEGIN

IF (clk1hz'event AND clk1hz='1') THEN IF(count1=\ELSE count1<= ; END IF; END IF; END PROCESS;

p2:PROCESS( ) BEGIN

CASE count1 IS

WHEN\

WHEN\WHEN\WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN OTHERS=>NULL; END CASE; END PROCESS;

END ARCHITECTURE beha;

三、问答题

1. 什么是数字系统的自下至上的设计方法?什么是数字系统自上至下的设计方法?各自

的特点是什么? 2. PLD电路的表述方法?

3. 可编程逻辑器件的一般设计流程是什么? 4. 什么是在系统可编程技术?它有什么特点?

5. 与传统的测试技术相比,边界扫描技术有和优点? 6. 什么是基于乘积项的可编程逻辑结构? 7. 什么是基于查找表的可编程逻辑结构? 8. 基于MAX+plus II的设计流程? 9. 基于Quartus II的设计流程?

10. 什么是VHDL语言?用VHDL语言设计数字系统有些什么优点? 11. VHDL语言定义的标准类型有哪些? 12. 什么叫对象?对象有哪几个类型? 13. 哪三种方法可以用来进行类型转换? 14. 试问下面3个VHDL语句是否等效:

① a<=NOT b AND c OR d (1) ② a<=(NOT b AND c ) OR d (2) ③ a<=NOT b AND (c OR d ) (3)

15. 什么叫进程?简述进程的工作方式? 16. 什么叫模块?如何区分模块与进程? 17. 配置语句的书写格式是怎样的? 18. 配置说明中的映射有哪两种方法?

19. 什么是库、程序包、子程序、过程调用、函数调用? 20. 怎样用VHDL语言描述时钟clk信号的上升沿? 21. 怎样用VHDL语言描述时钟clk信号的下降沿? 22. 怎样用VHDL语言描述同步复位信号? 23. 怎样用VHDL语言描述异步复位信号? 24. 为什么要层次化设计?

25. Moore型状态机和Mealy型状态机有什么相同和不同?