NRF24L01通信协议
#ifndef _RF_H_ #define _RF_H_
//****************************************************************// //define port
#define PORT_DIR_CSN DDRB #define PORT_DIR_SCK DDRB #define PORT_DIR_MOSI DDRB #define PORT_DIR_CE DDRD #define PORT_DIR_MISO DDRB #define PORT_DIR_IRQ DDRD
#define PORT_OUT_CSN PORTB #define PORT_OUT_SCK PORTB #define PORT_OUT_MOSI PORTB #define PORT_OUT_CE PORTD #define PORT_OUT_MISO PORTB #define PORT_OUT_IRQ PORTD
#define PORT_IN_MISO PINB #define PORT_IN_IRQ PIND
#define BIT_nRF24L01_CSN BIT2 #define BIT_nRF24L01_SCK BIT7 #define BIT_nRF24L01_MOSI BIT5 #define BIT_nRF24L01_CE BIT4 #define BIT_nRF24L01_MISO BIT6 #define BIT_nRF24L01_IRQ BIT2
#define RF_CSN_IO_OUT SETBIT(PORT_DIR_CSN, BIT_nRF24L01_CSN) #define RF_SCK_IO_OUT SETBIT(PORT_DIR_SCK, BIT_nRF24L01_SCK) #define RF_MOSI_IO_OUT SETBIT(PORT_DIR_MOSI, BIT_nRF24L01_MOSI) #define RF_CE_IO_OUT SETBIT(PORT_DIR_CE, BIT_nRF24L01_CE) #define RF_MISO_IO_IN CLEARBIT(PORT_DIR_MISO, BIT_nRF24L01_MISO) #define RF_IRQ_IO_IN CLEARBIT(PORT_DIR_IRQ, BIT_nRF24L01_IRQ)
#define nRF24L01_CSNH SETBIT(PORT_OUT_CSN, BIT_nRF24L01_CSN) #define nRF24L01_CSNL CLEARBIT(PORT_OUT_CSN, BIT_nRF24L01_CSN)
#define nRF24L01_SCKH SETBIT(PORT_OUT_SCK, BIT_nRF24L01_SCK) #define nRF24L01_SCKL CLEARBIT(PORT_OUT_SCK, BIT_nRF24L01_SCK)
#define nRF24L01_MOSIH SETBIT(PORT_OUT_MOSI, BIT_nRF24L01_MOSI) #define nRF24L01_MOSIL CLEARBIT(PORT_OUT_MOSI, BIT_nRF24L01_MOSI)
#define nRF24L01_CEH SETBIT(PORT_OUT_CE, BIT_nRF24L01_CE) #define nRF24L01_CEL CLEARBIT(PORT_OUT_CE, BIT_nRF24L01_CE)
#define nRF24L01_MISOH SETBIT(PORT_OUT_MISO, BIT_nRF24L01_MISO)
#define nRF24L01_MISOL CLEARBIT(PORT_OUT_MISO, BIT_nRF24L01_MISO)
#define nRF24L01_IRQH SETBIT(PORT_OUT_IRQ, BIT_nRF24L01_IRQ) #define nRF24L01_IRQL CLEARBIT(PORT_OUT_IRQ, BIT_nRF24L01_IRQ)
#define nRF24L01_MISO CHECKBIT(PORT_IN_MISO, BIT_nRF24L01_MISO) #define nRF24L01_IRQ CHECKBIT(PORT_IN_IRQ, BIT_nRF24L01_IRQ)
//****************************************************************// //data and add width
#define TX_ADR_WIDTH 5 // 5 bytes TX(RX) address width #define TX_PLOAD_WIDTH 20 // 16 bytes TX payload
#define RX_ADR_WIDTH 5 // 5 bytes TX(RX) address width #define RX_PLOAD_WIDTH 20 // 16 bytes TX payload
unsigned char txBuf[TX_PLOAD_WIDTH]; unsigned char rxBuf[RX_PLOAD_WIDTH];
unsigned char TX_ADDRESS[TX_ADR_WIDTH] = {0x34,0x43,0x10,0x10,0x01}; // Define a static TX address
unsigned char RX_ADDRESS[RX_ADR_WIDTH] = {0x34,0x43,0x10,0x10,0x01}; // Define a static RX address
//****************************************************************// // SPI(nRF24L01) commands
#define READ_REG 0x00 // Define read command to register #define WRITE_REG 0x20 // Define write command to register #define RD_RX_PLOAD 0x61 // Define RX payload register address #define WR_TX_PLOAD 0xA0 // Define TX payload register address #define FLUSH_TX 0xE1 // Define flush TX register command #define FLUSH_RX 0xE2 // Define flush RX register command
#define REUSE_TX_PL 0xE3 // Define reuse TX payload register command
//#define NOP 0xFF // Define No Operation, might be used to read status register //***************************************************// // SPI(nRF24L01) registers(addresses)
#define CONFIG 0x00 // 'Config' register address
#define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address #define EN_RXADDR 0x02 // 'Enabled RX addresses' register address #define SETUP_AW 0x03 // 'Setup address width' register address #define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address #define RF_CH 0x05 // 'RF channel' register address #define RF_SETUP 0x06 // 'RF setup' register address #define STATUS 0x07 // 'Status' register address
#define OBSERVE_TX 0x08 // 'Observe TX' register address #define CD 0x09 // 'Carrier Detect' register address
#define RX_ADDR_P0 0x0A // 'RX address pipe0' register address #define RX_ADDR_P1 0x0B // 'RX address pipe1' register address #define RX_ADDR_P2 0x0C // 'RX address pipe2' register address #define RX_ADDR_P3 0x0D // 'RX address pipe3' register address #define RX_ADDR_P4 0x0E // 'RX address pipe4' register address #define RX_ADDR_P5 0x0F // 'RX address pipe5' register address #define TX_ADDR 0x10 // 'TX address' register address
#define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address #define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address #define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address #define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address #define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address #define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address #define FIFO_STATUS 0x17 // 'FIFO Status Register' register address #define MAX_RT 0x10 // Max #of TX retrans interrupt #define TX_DS 0x20 // TX data sent interrupt #define RX_DR 0x40 // RX data received
//----------------------------------------------------------------------------- #define SW_MODE 1 #define HW_MODE 2
#define RF_MODE SW_MODE
void delay(void)// { NOP(); NOP(); NOP(); NOP(); NOP();