附录
一、12/24小时数字时钟VHDL设计
1，系统顶层逻辑图：
时序仿真波形
管脚定义以及锁定
2，分频模块。
①各个分频模块的模块图：
②，分别对应的仿真波形：
③50mhz分频至1k模块代码：
library ieee;
use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity wh4574_divto1k is port(clk50m:in std_logic; clk1k:out std_logic); end wh4574_divto1k;
architecture behav of wh4574_divto1k is signal count1:std_logic_vector(14 downto 0);
signal count2:std_logic; signal co:std_logic; begin process(clk50m) begin
if clk50m'event and clk50m='1' then if count1=\then count1<=\ co<='1'; else
count1<=count1+'1'; co<='0'; end if; end if;
end process; process(co) begin
if co'event and co='1' then count2<=not count2; end if; end process; clk1k<=count2; end behav;
50mhz分频至2k模块代码： library ieee;
use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity wh4574_divto2k is port(clk50m:in std_logic; clk2k:out std_logic); end wh4574_divto2k;
architecture behav of wh4574_divto2k is signal count1:std_logic_vector(13 downto 0);
signal count2:std_logic; signal co:std_logic; begin process(clk50m)
begin
if clk50m'event and clk50m='1' then if count1=\then count1<=\ co<='1'; else
count1<=count1+'1'; co<='0'; end if; end if;
end process; process(co) begin
if co'event and co='1' then count2<=not count2; end if; end process; clk2k<=count2; end behav;
1k分频至5hz代码： library ieee;
use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity wh4574_div1kto5 is port(inclk1k:in std_logic; clk5hz:out std_logic); end wh4574_div1kto5;
architecture behav of wh4574_div1kto5 is signal count1:std_logic_vector(6 downto 0);
signal count2:std_logic; signal co:std_logic; begin process(inclk1k) begin
if inclk1k'event and inclk1k='1' then if count1=\then count1<=\ co<='1';
else
count1<=count1+'1'; co<='0'; end if; end if;
end process; process(co) begin
if co'event and co='1' then count2<=not count2; end if; end process; clk5hz<=count2; end behav;
5分频代码： library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity wh4574_div_5 is port(clk:in std_logic; q:out std_logic); end wh4574_div_5;
architecture behav of wh4574_div_5 is signal count:std_logic_vector(2 downto 0); begin
process(clk) begin
if clk'event and clk='1' then if count=\ count<=\ q<='1'; else
count<=count+1; q<='0'; end if; end if;
end process; end behav;