基于FPGA的正弦信号发生器设计—毕业设计

--波形ROM

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ROM IS

PORT(ADDER:IN STD_LOGIC_VECTOR(7 DOWNTO 0); DAOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY ROM;

ARCHITECTURE ART OF ROM IS BEGIN

PROCESS(ADDER) IS BEGIN CASE ADDER IS

when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\

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when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\

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when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\

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when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\

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when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\

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