三 verilog代码和仿真
module S4_LVDS_TEST( clk, rst_n, rx_data, rx_inclock, tx_data, tx_outclock );
input clk; input rst_n; input rx_data; input rx_inclock; output tx_data; output tx_outclock;
wire [3:0] rx_dataout; wire rx_dataout_clk; wire tx_coreclock; wire tx_locked;
wire rx_dpa_locked; wire rx_locked;
ALTLVDS_RS U_ALTLVDS_RX( .rx_in (rx_data), .rx_inclock (rx_inclock), .rx_out (rx_dataout), .rx_outclock (rx_dataout_clk), .rx_fifo_reset (!rst_n), .rx_reset (!rst_n), .rx_dpa_locked (rx_dpa_locked), .rx_locked (rx_locked) );
reg [3:0] test_data1;
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
test_data1 <= 4'b0; else test_data1 <= test_data1+1'b1; end
ALTLVDS_TX1 U_ALTLVDS_TX1( .tx_in (test_data1), .tx_inclock (clk), .tx_out (tx_data), .tx_outclock (tx_outclock), .tx_coreclock (tx_coreclock), .tx_locked (tx_locked) );
endmodule