时间以使振荡器重启动并稳定工作。
程序存储器的加密 ：AT89S52可使用对芯片上的3个加密位进行编程（P）或不编程（U）来得到如下表所示的功能： 加密位保护功能表 程序加密位 LB1 1 2 3 4 U P P P LB2 U U P P LB3 U U U P 没有程序保护功能 禁止从外部程序存储器中执行MOVC指令读取内部程序存储器的内容 除上表功能外，还禁止程序校验 除以上功能外，同时禁止外部执行 保护类型 当加密位LB1被编程时，在复位期间，EA端的逻辑电平被采样并锁存，如果单片机上电后一直没有复位，则锁存起的初始值是一个随机数，且这个随机数会一直保持到真正复位为止。为使单片机能正常工作，被锁存的EA电平值必须与该引脚当前的逻辑电平一致。此外，加密位只能通过整片擦除的方法清除。 FLASH闪速存储器的编程：at89s52单片机内部有4K字节的FLASH PEROM,这个FLASH存储阵列出厂时已处于擦除状态（即所有存储单元的内容均为FFH），用户随时可对其进行编程。编程接口可接收高电平（+12V）或低电平（VCC）的允许编程信号，低电平编程模式适合于用户再线编程系统，而高电平编程模式可与通用EPROM编程器兼容。
AT89S52单片机中，有些属于低电压编程方式，而有些则是高电平编程方式，用户可从芯片上的型号和读取芯片内的签名字节获得该信息，见下表。
芯片顶面标识 签名字节 Vpp=12v at89s52 xxxx yyww (030H)=1EH (031H)=51H (032H)=FFH Vpp=5v at89s52 xxxx-5 yyww (030H)=1EH (031H)=51H (032H)=05H AT89S52的程序存储器阵列是采用字节写入方式编程的，每次写入一个字节，要对整个芯片内的PEROM程序存储器写入一个非空字节，必须使用片擦除的方式将整个存储器的内容清除。 编程方法：
编程前，需按表1、图3和图4所示设置好地址，数据及控制信号， at89s52编程方法如下：
1.在地址线上加上要编程单元的地址信号。 2.在数据线上加上要写入的数据字节。 3.激活相应的控制信号。
4.在高电压编程方式时，将^EA/VPP端加上+12V编程电压。
5.每对FLASH存储阵列写入一个字节或每写入一个程序加密位，加上一个ALE/^PROG编程脉冲，改变编程单元的地址和写入的数据，重复1—5步骤，直到全部文件编程结束。每个字节写入周期是自身定时地，通常约为1.5ms。 数据查询：at89s52单片机用数据查询方式来检测一个写周期是否结束，在一个写周期中，如需要读取最后写入的那个字节，则读出的数据的最高位（P0.7）是原来写入字节最高位的反码。写周期完成后，有效的数据就会出现在所有输出端上，此时，可进入下一个字节的写周期，写周期开始后，可在任意时刻进行数据查询。
READY/^BUSY：字节编程的进度可通过“RDY/^BSY”输出信号监测，编程期间，ALE变为高电平“H”后P3.4(RDY/^BSY)端电平被拉低，表示正在编程状态（忙状态）。编程完成后，P3.4变为高电平表示准备就绪状态。
程序校验：如果加密位LB1、LB2没有进行编程，则代码数据可通过地址和数据线读回原编写的数据。加密位不可能直接变化。证实加密位的完成通过观察它们的特点和能力。
芯片擦除：利用控制信号的正确组合（表1）并保持ALE/^PROG引脚10ms的低电平脉冲宽度即可将PEROM阵列（4k字节）整片擦除，代码阵列在擦除操作中将任何非空单元写入“1”，这步骤需要再编程之前进行。
读片内签名字节：at89s52单片机内有3个签名字节，地址为030H、031H和032H。用于声明该器件的厂商、型号和编程电压。读签名字节的过程和单元030H、031H和032H的正常校验相仿，只需将P3.6和P3.7保持低电平，返回值意义如下：
（030H）=1EH声明产品由ATMEL公司制造。 （031H）=51H声明为at89s52单片机。 （032H）=FFH声明为12V编程电压。 （032H）=05H声明为5V编程电压。
编程接口：采用控制信号的正确组合可对FLASH闪速存储阵列中的每一代码字节进行写入和存储器的整片擦除，写操作周期是自身定时的，初始化后它将自动定时到操作完成。
AT89S52 single chip microcomputer
The at89s52 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51?
instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel at89s52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
Features:
? Compatible with MCS-51? Products
? 4K Bytes of In-System Reprogrammable Flash Memory ? Endurance: 1,000 Write/Erase Cycles ? Fully Static Operation: 0 Hz to 24 MHz ? Three-Level Program Memory Lock ? 128 x 8-Bit Internal RAM ? 32 Programmable I/O Lines ? Two 16-Bit Timer/Counters ? Six Interrupt Sources
? Programmable Serial Channel
? Low Power Idle and Power Down Modes
The at89s52 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level
interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the at89s52 is designed with static logic for operation down to zero
frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description:
VCC Supply voltage. GND Ground. Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.
Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.
Port 0 also receives the code bytes during Flash programming, and outputs the
code bytes during program verification. External pullups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses
(MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features of the at89s52 as listed below:
Port pin alternate functions P3.0 rxd (serial input port) Port 3 also P3.1 txd (serial output port) receives some P3.2 ^int0 (external interrupt0) control signals for P3.3 ^int1 (external interrupt1) Flash programming P3.4 t0 (timer0 external input) and verification.
P3.5 t1 (timer1 external input) RST
P3.6 ^WR (external data memory write Reset input. A
strobe) high on this pin for
P3.7 ^rd (external data memory read strobe) two machine cycles
while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address