VHDL语法格式

when s1 => dout <= \ when s2 => dout <= \ when s3 => dout <= \ end case; end process; end;

begin

if reset = '1' then state <= s0;

elsif rising_edge ( clock ) then case state is

when s0 => if din = '1' then state <= s1;

二进程mealy状态机

library ieee;

use ieee.std_logic_1164.all;

entity mealy_1 is port ( reset : in std_logic; clock : in std_logic; din : in std_logic;

dout : out std_logic_vector ( 2 downto 0 ) ); end entity;

architecture statemachine of mealy_1 is type state_type is ( s0, s1, s2, s3 ); signal state : state_type; begin

process ( reset, clock ) -- 变换状态

end if; when s1 => if din = '1' then state <= s2; end if; when s2 => if din = '1' then state <= s3; end if; when s3 => if din = '1' then state <= s0; else

state <= s1; end if; end case; end if; end process;

process ( state, din ) -- 输出

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VHDL语法格式

begin

case state is

when s0 => if din='0' then dout <=\ else

dout <=\ end if; when s1 => if din='0' then dout <=\ else

dout <=\ end if; when s2 => if din='0' then dout <=\ else

dout <=\ end if; when s3 => if din='0' then dout <=\ else

dout <=\ end if; end case;

end process; end architecture;

三进程mealy状态机

library ieee;

use ieee.std_logic_1164.all;

entity mealy_2 is

port ( reset : in std_logic; clock : in std_logic; din : in std_logic;

dout : out std_logic_vector( 2 downto 0 ) ); end entity;

architecture statemachine of mealy_2 is type state_type is ( s0, s1, s2, s3 ); signal presentstate : state_type; signal nextstate : state_type; begin

process ( reset, clock ) -- 更新当前状态 begin

if reset = '1' then presentstate <= s0;

17

VHDL语法格式

elsif rising_edge ( clock ) then presentstate <= nextstate; end if; end process;

process ( presentstate, din ) -- 生成次态 begin

case presentstate is when s0 => if din ='1' then nextstate <= s1; else

nextstate <= s0; end if; when s1 => if din ='1' then nextstate <= s2; else

nextstate <= s1; end if; when s2 => if din ='1' then nextstate <= s3; else

nextstate <= s2; end if;

when s3 => if din = '1' then nextstate <= s0; else

nextstate <= s1; end if; end case; end process;

process ( presentstate, din ) -- 输出 begin

case presentstate is

when s0 => if din = '0' then dout <= \ else

dout <= \ end if;

when s1 => if din = '0' then dout <= \ else

dout <= \ end if;

when s2 => if din = '0' then dout <= \ else

18

VHDL语法格式

dout <= \ end if;

when s3 => if din = '0' then dout <= \ else

dout <= \ end if; end case; end process; end;

entity traffic_light is

port ( sensor : in std_logic; clock : in std_logic; red_light : out std_logic; green_light : out std_logic; yellow_light : out std_logic ); end traffic_light;

architecture simple of traffic_light is

type t_state is ( red, green, yellow ); -- 定义枚举状态

用状态机设计交通灯之一

-- -- -- -- -- -- -- 3 --

个进程的状态机。

这是一个简单的状态机设计实例,根据时钟变换路口 的红,绿,黄三个信号灯,从程序中可以看出,时钟 的周期至少应为,例如30秒。

这个状态机程序的程序的特点是,有2个进程,一个 进程负责生成次级状态和输出当前状态的输出信号, 一个进程负责更新当前状态。

除了本例中的2个进程的状态机外,还有1个进程与

signal present_state : t_state; -- 中间信号 signal next_state : t_state; begin

-- 以下过程生成次级状态并根据状态变换信号灯 process ( present_state, sensor) begin

case present_state is

when green => red_light <= '0'; green_light <= '1'; yellow_light <= '0'; next_state <= yellow; when red => red_light <= '1';

19

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

VHDL语法格式

green_light <= '0'; yellow_light <= '0'; if sensor = '1' then

next_state <= green; -- 无人 else

next_state <= red; -- 有人 end if;

when yellow => red_light <= '0'; green_light <= '0'; yellow_light <= '1'; next_state <= red; end case; end process;

-- 以下过程更新当前状态

process begin

wait until clock'event and clock = '1'; present_state <= next_state; end process; end simple;

entity lighta is

port ( clock,din : in bit; dout : out bit ); end lighta;

architecture behaviour of lighta is type state_type is ( s0, s1, s2, s3 ); signal present_state : state_type; signal next_state : state_type; begin fb_logic:

process ( present_state, din ) -- 变换下一个状态并输出 begin

case present_state is when s0 => if din = '0' then dout <= '0'; next_state <= s0; else

dout <= '1';

用状态机设计交通灯之二

-- mealy type state machine example

next_state <= s2; end if;

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VHDL语法格式

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