ENTITY mux21a IS
PORT ( a, b : IN BIT; s : IN BIT; y : OUT BIT ); END ENTITY mux21a;
ARCHITECTURE one OF mux21a IS BEGIN
PROCESS (a,b,s)
BEGIN IF s = '0' THEN y <= a ; ELSE y <= b ; END IF; END PROCESS; END ARCHITECTURE one ;
3-8译码器。LIBRARY ieee;
USE ieee.std_logic_1164.ALL; ENTITY decoder3_8 IS PORT(A, B,C,G1,G2A,G2B: IN STD_LOGIC;
Y:OUT
STD_LOGIC_VECTOR (7 DOWNTO 0)); END decoder3_8;
ARCHITECTURE fun OF decoder3_8 IS
SIGNAL indata: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN M<= \；
indata <= C&B&A; encoder: PROCESS (indata, G1, G2A,G2B)
BEGIN
IF (G1='1' AND G2A='0' AND G2B='0') THEN CASE indata IS WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \
WHEN \
WHEN OTHERS =>Y<=\ END CASE;ELSE
Y<=\
END IF;END PROCESS encoder; END fun;
实验三 十进制计数器
USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY counter IS
PORT(clr,en,clk: IN STD_LOGIC; co : OUT STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END counter;
ARCHITECTURE counter1 OF counter IS
SIGNAL qs: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ca: STD_LOGIC; BEGIN M<= \
PROCESS(clk)
-- VARIABLE q10:INTEGER; BEGIN IF(rising_edge(clk)) THEN IF(clr='1') THEN qs<=\ ELSIF(en='1') THEN
IF(qs=\
ca<='1'; ELSE qs <= qs+1; ca<='0'; END IF; END IF;
END IF; END PROCESS; Q<= qs; co<= ca AND en;
END counter1; 1位全加半加器：
ENTITY half_adder IS
PORT (a,b : IN STD_LOGIC; s,co: OUT STD_LOGIC); END half_adder;
ARCHITECTURE half1 OF half_adder IS SIGNAL c,d : STD_LOGIC; BEGIN c<=a OR b;
d<=a NAND b; co<=NOT d; s<=c AND d; END half1;
全加器：
ENTITY fulladder IS
PORT (a, b, cin: IN STD_LOGIC; sum, co : OUT STD_LOGIC; M : out std_logic_vector(3 downto 0)); END fulladder;
ARCHITECTURE full1 OF fulladder IS COMPONENT half_adder PORT (a,b :IN STD_LOGIC; s,co:OUT STD_LOGIC); END COMPONENT ;
SIGNAL u0_co,u0_s,u1_co : STD_LOGIC; BEGIN M <= \
U0: half_adder PORT MAP(a,b,u0_s,u0_co); U1: half_adder PORT MAP(u0_s, cin, sum, u1_co); co<=u0_co OR u1_co; END full1;
实验五 数控分频器的设计 ENTITY PULSE IS
PORT ( CLK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); FOUT : OUT STD_LOGIC ); END; ARCHITECTURE one OF PULSE IS SIGNAL FULL : STD_LOGIC; BEGIN P_REG: PROCESS(CLK)
VARIABLE CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
IF CLK'EVENT AND CLK = '1' THEN IF CNT8 = \
CNT8 := D; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8
FULL <= '1'; --同时使溢出标志信号FULL输出为高电平 ELSE CNT8 := CNT8 + 1; --否则继续作加1计数
FULL <= '0'; --且输出溢出标志信号FULL为低电平 END IF;END IF; END PROCESS P_REG ; P_DIV: PROCESS(FULL)
VARIABLE CNT2 : STD_LOGIC;
BEGIN IF FULL'EVENT AND FULL = '1' THEN CNT2 := NOT CNT2;--如果溢出标志信号 FULL为高电平，D触发器输出取反
IF CNT2 = '1' THEN FOUT <= '1'; ELSE FOUT <= '0'; END IF; END IF; END PROCESS P_DIV ; END;
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