鍩轰簬
CPLD
鐨勪竷娈垫樉绀鸿瘧鐮佸櫒璁捐
1.
鏂板缓宸ョ▼銆?/p>
鈶?/p>
涓轰究浜庡伐绋嬬鐞嗗湪妗岄潰鏂板缓鏂囦欢澶广�?/p>
鍙屽嚮妗岄潰
Quartus
鈪″浘鏍囷紝鐐瑰嚮
Greate a New Project
鈥旓紴
Next
鈥旓紴寮瑰嚭绐楀彛
鈶?/p>
new of project
锛?/p>
seg7_4
鈶?/p>
entity name
锛?/p>
seg7_4
锛堣蒋浠堕粯璁や笌涓婅堪
new of project
涓�鑷达級
鈶?/p>
next
鈥旓紴
寮瑰嚭鈥滅洰鏍囧櫒浠惰缃�濈獥鍙?/p>
Family
锛?/p>
MAX
鈪?/p>
锛?/p>
MAX7000S
锛?/p>
鍣ㄤ欢鍨嬪彿锛?/p>
EPM240T100C5
锛?/p>
EPM7128SLC84-15
锛?/p>
鈶?/p>
next
鈥旓紴
next
鈥旓紴
finish
鎴栬�?/p>
杩涘叆涓荤晫闈紝
File
鈥旓紴
New Project Wizard
鈥旓紴
Next
鈥旓紴
寮瑰嚭绐楀彛
閲嶅涓婅堪鈶♀憿鈶ｂ懁銆?/p>
2.
缂栬緫涓冩鏄剧ず璇戠爜鍣ㄧ殑
VHDL
鏂囦欢銆?/p>
涓昏彍鍗?/p>
File
鈥旓紴
New
鈥旓紴
閫夋嫨
VHDL
File
鈥旓紴
OK
鈥旓紴
杩涘叆
VHDL
鏂囨湰缂栬緫绐楋紝
鍦ㄥ叾涓敭鍏ヤ笅鍒楄璁℃枃浠讹紙
Copy
鍗冲彲锛?/p>
銆?/p>
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
Entity seg7_4 is
PORT ( BCD_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --
杈撳叆鍥涗綅
BCD
鐮?/p>
SG_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --
杈撳嚭涓冧綅瀛楀舰鐮?/p>
END;
ARCHITECTURE one OF seg7_4 IS
BEGIN
PROCESS(BCD_in)
BEGIN
CASE BCD_in IS
WHEN "0000" => SG_out <= "0111111";
WHEN "0001" => SG_out <= "0000110";
WHEN "0010" => SG_out <= "1011011";
WHEN "0011" => SG_out <= "1001111";
WHEN "0100" => SG_out <= "1100110";
WHEN "0101" => SG_out <= "1101101";
WHEN "0110" => SG_out <= "1111101";