榫欐簮鏈熷垔缃?/p>
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FPGA
搴旂敤鎶�鏈強鍏跺彂灞?/p>
浣滆�咃細宸﹂獝
鏉ユ簮锛氥�婂ぇ涓滄柟銆?/p>
2016
骞寸
04
鏈?/p>
鎽?/p>
瑕侊細
FPGA
鎶�鏈湪鐢靛瓙璁捐棰嗗煙搴旂敤骞挎硾锛岄�愭笎鎴愪负璁捐瀹炵幇鐢靛瓙绯荤粺鐨勪富瑕佹墜娈点�傛湰
鏂囦富瑕佷粙缁嶄簡
FPGA
鎶�鏈殑鐗圭偣銆佽璁℃祦绋嬪強鍏跺彂灞曡秼鍔裤�?/p>
鍏抽敭璇嶏細鐜板満鍙紪绋嬮棬闃靛垪锛?/p>
FPGA
锛涜璁℃祦绋?/p>
1
寮曡█
鍦ㄦ暟瀛楃數璺璁′腑锛?/p>
FPGA
锛?/p>
Field Programmable Gate Array
锛岀幇鍦哄彲缂栫▼闂ㄩ樀鍒楋級鎶�鏈緱
鍒拌秺鏉ヨ秺骞挎硾鐨勫簲鐢ㄣ�傜敤鎴峰彲浠ラ�氳繃鏀瑰彉閰嶇疆淇℃伅瀵瑰叾鍔熻兘杩涜閲嶆柊瀹氫箟锛屾潵婊¤冻璁捐瑕佹眰銆?/p>
FPGA
鍏锋湁鍙紪绋嬨�侀珮闆嗘垚搴︺�侀珮閫熺瓑浼樼偣銆傚叾鍙紪绋嬬壒鎬у甫鏉ヤ簡鐢佃矾璁捐鐨勭伒娲绘�э紝缂╃煭浜?/p>
浜у搧鐮斿彂鍛ㄦ湡銆?/p>
FPGA
鎶�鏈凡缁忔垚涓虹數瀛愬伐绋嬪笀璁捐瀹炵幇鐢靛瓙绯荤粺鐨勪富瑕佹墜娈点�?/p>
2 FPGA
绠�浠?/p>
FPGA
鏄?/p>
PAL
锛?/p>
Programmable Array Logic
锛屽彲缂栫▼闃靛垪閫昏緫锛夈�?/p>
GAL
锛?/p>
Generic Array
Logic
锛岄�氱敤闃靛垪閫昏緫锛夈�?/p>
PLD
锛?/p>
Programmable Logic Device
锛屽彲缂栫▼閫昏緫鍣ㄤ欢锛夌瓑鍙紪绋嬪櫒浠?/p>
鐨勫熀纭�涓婂彂灞曡捣鏉ョ殑銆?/p>
FPGA
鏄竴绉嶅崐瀹氬埗涓撶敤闆嗘垚鐢佃矾锛?/p>
ASIC
锛夛紝瀹冪殑鍑虹幇鏃㈣В鍐充簡鍏ㄥ畾鍒?/p>
ASIC
鐨勪笉瓒筹紝鍙堝厠鏈嶄簡鍘熸湁
PLD
鐢佃矾鏁版湁闄愮殑缂虹偣銆?/p>
FPGA
閲囩敤浜嗛�昏緫鍗曞厓闃靛垪
LCA
锛?/p>
Logic Cell Array
锛夌殑缁撴瀯锛屽唴閮ㄥ寘鎷彲閰嶇疆閫昏緫妯″潡
CLB
锛?/p>
Configurable Logic Block
锛夈�佽緭鍏ヨ緭鍑烘ā鍧?/p>
IOB
锛?/p>
Input Output Block
锛夊拰鍐呴儴杩炵嚎
锛?/p>
Interconnect
锛変笁閮ㄥ垎銆?/p>
FPGA
鐨勪富瑕佺壒鐐规湁锛?/p>
锛?/p>
1
锛夐噰鐢?/p>
FPGA
璁捐
ASIC
鐢佃矾锛岀敤鎴蜂笉闇�瑕佹姇鐗囩敓浜э紝灏辫兘寰楀埌鍚堢敤鐨勮姱鐗囥�?/p>
锛?/p>
2
锛?/p>
FPGA
鍐呴儴鏈変赴瀵岀殑瑙﹀彂鍣ㄥ拰
I/O
寮曡剼銆?/p>
锛?/p>
3
锛?/p>
FPGA
鏄?/p>
ASIC
鐢佃矾涓璁″懆鏈熸渶鐭�佸紑鍙戣垂鐢ㄦ渶浣庛�侀闄╂渶灏忕殑鍣ㄤ欢涔嬩竴銆?/p>
锛?/p>
4
锛?/p>
FPGA
閲囩敤楂橀�?/p>
CHMOS
宸ヨ壓锛屽姛鑰椾綆锛屽彲浠ヤ笌
CMOS
銆?/p>
TTL
鐢靛钩鍏煎銆?/p>
锛?/p>
5
锛?/p>
FPGA
鍏锋湁璁捐鐏垫椿銆佸紑鍙戝懆鏈熺煭銆佸姛鑰椾綆绛夌壒鐐广�?/p>