1
锛庢暟瀛楃數璺璁′腑閫氬父閲囩敤鐨勪袱绉嶈璁℃柟娉曪細
鍜?/p>
銆?/p>
2
锛庡０鏄庝竴涓悕涓?/p>
reg_a
鐨?/p>
32
浣嶅瘎瀛樺櫒锛屼笖鍏剁
0
浣嶄负鏈�楂樻湁鏁堜綅锛?/p>
锛?/p>
鍐嶅０鏄庝竴涓惈鏈?/p>
256
涓瓧鐨勫瓨鍌ㄥ櫒
MEM
锛屾瘡涓瓧鐨勫瓧闀夸负
32
浣嶏細
銆?/p>
3
锛庝粠妯″潡鍐呴儴鏉ョ湅锛岃緭鍏ョ鍙ｅ繀椤讳负
鏁版嵁绫诲瀷锛涜緭鍑虹鍙ｅ彲浠ユ槸
鏁版嵁绫诲瀷銆備粠妯″潡澶栭儴鏉ョ湅锛岃緭鍏ョ鍙ｅ彲浠ヤ负
鏁版嵁绫诲瀷锛涜緭鍑虹鍙ｅ繀椤绘槸
鏁版嵁绫诲瀷銆?/p>
assign
璇彞涓璧嬪�肩殑淇″彿蹇呴』鏄?/p>
鏁版嵁绫诲瀷锛?/p>
always
鍜?/p>
initial
璇彞鍧椾腑
琚祴鍊肩殑淇″彿蹇呴』鏄?/p>
鏁版嵁绫诲瀷锛?/p>
4
锛庡湪瀵规ā鍧楄皟鐢?/p>
锛堝疄渚嬪紩鐢級鐨勬椂鍊欙紝鍙互浣跨敤涓ょ鏂规硶灏嗗畾涔夌鍙ｄ笌澶栭儴鐜杩炴帴璧锋潵锛?/p>
鍜?/p>
5
锛庡熀鏈殑閫昏緫闂ㄥ彲浠ュ垎涓轰袱绫伙細
鍜?/p>
銆?/p>
6
锛庤嫢
A=4
鈥?/p>
b0011;B=4
鈥?/p>
b0100,
鍒?/p>
A&&B=
,{A ,~B}=
銆?/p>
7
锛?/p>
Verilog HDL
鐢ㄤ袱涓鍙峰垎鍒〃绀轰笉纭畾鍊煎拰楂橀樆鍊硷紝涓嶇‘瀹氬�肩敤
琛ㄧず锛岄珮闃诲�肩敤
琛ㄧず銆?/p>
8.
鑻ヤ俊鍙峰彂鐢熻烦鍙橈紝鍏抽敭瀛?/p>
鎸囨鍚戣烦鍙橈紝
鎸囪礋鍚戣烦鍙樸�?/p>
9.
鍏抽敭瀛?/p>
鍜?/p>
灏嗗鏉¤鍙ョ粍鎴愰『搴忓潡锛涜�屽苟琛屽潡鐢?/p>
鍏抽敭瀛?/p>
鍜?/p>
浣滀负寮�濮嬪拰缁撴潫鏍囧織銆?/p>
10.
濉啓涓嬮潰鐨勮鍙?/p>
reg FF1,FF2,FF3,output;
always @(posedge Clock)
begin