鐢靛瓙璁捐鑷姩鍖栧疄楠屾姤鍛?/p>
濮撳悕锛氳矾浼犳稕
瀛﹀彿锛?/p>
201215728
鏃堕棿
11-12
绗洓澶ц妭
鍦扮偣
S-5B208
涓冩鏁扮爜鏄剧ず璇戠爜鍣ㄨ璁?/p>
1.
瀹為獙鐩殑锛?/p>
瀛︿範
7
娈垫暟鐮佹樉绀鸿瘧鐮佸櫒璁捐锛屽涔?/p>
VHDL
鐨勫灞傛璁捐鏂规硶銆?/p>
2.
瀹為獙鍘熺悊锛?/p>
涓冩鏁扮爜绠＄敱
8
涓紙
a,b,c,d,e,f,g,dp
锛夋寜鐓т竴瀹氫綅缃帓鍒楃殑鍙戝厜浜屾瀬绠℃瀯鎴愶紝
閫氬父閲囧彇鍏遍槾鏋佹垨鑰呭叡闃虫瀬鐨勮璁★紝
灏?/p>
8
涓簩鏋佺鐨勫悓涓�鏋佹帴鍦ㄤ竴璧凤紝
閫氳繃鍒嗗埆
鎺у埗鍙﹀鐨?/p>
8
涓數鏋佺殑鐢靛钩锛屼娇浜屾瀬绠″閫氾紙鍙戝厜锛夋垨鎴锛堜笉鍙戝厜锛?/p>
銆?/p>
涓冩鏁扮爜鏄剧ず璇戠爜鍣ㄧ殑鍔熻兘灏辨槸鏍规嵁闇�瑕佹樉绀虹殑瀛楃锛?/p>
杈撳嚭鑳藉鎺у埗涓冩鏁扮爜绠?/p>
鏄剧ず鍑鸿瀛楃鐨勭紪鐮併�?/p>
3.
瀹為獙浠櫒锛?/p>
EDA6000
閫氱敤瀹為獙寮�鍙戠郴缁燂紝
P4
鐢佃剳
4.
瀹為獙鍐呭锛?/p>
1
锛夌敤
VHDL
璁捐
7
娈垫暟鐮佺鏄剧ず璇戠爜鐢佃矾锛屽苟鍦?/p>
VHDL
鎻忚堪鐨勬祴璇曞钩鍙颁笅瀵硅瘧鐮?/p>
鍣ㄨ繘琛屽姛鑳戒豢鐪燂紝缁欏嚭浠跨湡鐨勬尝褰€�?/p>
---------------------------------------------------------------------
绋嬪簭锛?/p>
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SMG IS
PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));