榫欐簮鏈熷垔缃?/p>
http://www.qikan.com.cn
I2C
锛?/p>
SPI
锛?/p>
SMI
锛?/p>
SMBus
涓茶鎺ュ彛瀹炵幇鏂?/p>
娉?/p>
浣滆�咃細搴峰
鍛ㄧ帀濞?/p>
鏉ユ簮锛氥�婁腑鍥界鎶�绾垫í銆?/p>
2014
骞寸
04
鏈?/p>
銆愭憳
瑕併�?/p>
I2C
銆?/p>
SPI
銆?/p>
SMI
锛?/p>
MDC
銆?/p>
MDIO
锛夈�?/p>
SMBus
绛夋帴鍙ｅ彈鏃堕挓棰戠巼鐨勯檺鍒讹紝鐩稿浜?/p>
楂橀�熻繍琛岀殑
CPU
鑺墖鏉ヨ鎺ュ彛杩愯閫熷害杈冩參銆備絾骞朵笉鏄墍鏈?/p>
CPU
鑺墖閮芥敮鎸佽繖浜涗覆琛屾帴鍙ｏ紝
鍦ㄥ緢澶氱郴缁熶腑闇�瑕佽В鍐?/p>
CPU
鑺墖涓庝覆琛屾帴鍙ｈ姱鐗囩殑浜掕仈闂銆傛湰鏂囨彁鍑轰笁绉?/p>
CPU
鑺墖涓庝覆琛?/p>
鎺ュ彛浜掕仈鏂规锛屽叾涓柟妗堜竴浣跨敤
CPU
鑺墖鐨?/p>
GPIO
鎺ュ彛涓庝覆琛屾帴鍙ｈ姱鐗囦簰鑱旓紝鏂规浜?/p>
CPU
鑺?/p>
鐗囬�氳繃
FPGA
鑺墖涓庝覆琛屾帴鍙ｈ姱鐗囬棿鎺ヤ簰鑱旓紝鏂规涓?/p>
FPGA
鐨?/p>
SOPC
鎶�鏈唬鏇?/p>
CPU
鑺墖涓庝覆
琛屾帴鍙ｈ姱鐗囦簰鑱斻�?/p>
銆愬叧閿瘝銆?/p>
I2C SPI SMI
锛?/p>
MDC
銆?/p>
MDIO
锛?/p>
SMBus FPGA SOPC
銆?/p>
Abstract
銆?/p>
I2C
锛?/p>
SPI
锛?/p>
SMI
锛?/p>
MDC
銆?/p>
MDIO
锛?/p>
and SMBus limited by the interface clock
frequency
锛?/p>
relative to the CPU chip for high-speed operation of the interface to run slower
锛?/p>
But not
all CPU chips support these serial interfaces
锛?/p>
in many systems interconnected issues need to be
resolved with the CPU chip and serial interface chip
锛?/p>
This paper proposes three CPU chip
interconnect solutions with serial interface
锛?/p>
Which program to use a CPU chip GPIO interface with
serial interface chip interconnect
锛?/p>
Option II CPU chip FPGA chip by indirect interconnection with
serial interface chip
锛?/p>
Option III FPGA SOPC technology instead of the CPU chip interconnect with a
serial interface chip.
銆?/p>
Key words
銆?/p>
I2C SPI SMI SMBus FPGA SOPC
涓轰簡鍑忓皬鑺墖鐨勪綋绉紝鍑忓皬甯冪嚎鐨勫鏉傚害锛屾彁楂樼郴缁熺殑鍙潬鎬т互鍙婇泦鎴愬害锛岃秺鏉ヨ秺澶氱殑鑺?/p>
鐗囬噰鐢ㄤ覆琛?/p>
I2C
鎺ュ彛銆?/p>
SPI
鎺ュ彛銆?/p>
SMI
锛?/p>
MDC
銆?/p>
MDIO
锛夋帴鍙ｃ�?/p>
SMBus
鎺ュ彛绛夛紱渚嬪
EEPROM
銆?/p>
FLASH
銆佷互澶綉
PHY
鑺墖锛岄攣鐩哥幆鑺墖锛屾俯搴︽祴閲忚姱鐗囥�佸厜鐢佃浆鎹㈡ā鍧楃瓑銆?/p>
涓茶鎺ュ彛浣跨敤绠�鍗曪紝鐢?/p>
2
鍒?/p>
4
鏍逛俊鍙峰氨鍙互瀹屾垚鑺墖鍒濆鍖栥�侀厤缃�佽繍琛岀姸鎬佹煡璇㈢瓑鎿?/p>
浣溿�備絾鍦ㄥ悇绉嶇郴缁熶腑锛屼覆琛屾帴鍙ｈ繍琛岄�熺巼杈冩參锛屼覆琛屾帴鍙ｈ姱鐗囦笌楂橀�熺殑
CPU
鑺墖濡備綍浜掕仈鏄?/p>
涓�涓簾寰呰В鍐崇殑闂銆?/p>
1 I2C
銆?/p>
SPI
銆?/p>
SMI
銆?/p>
SMBus
涓茶鎺ュ彛绠�浠?/p>