8
浣嶆暟閫昏緫宸︾Щ锛屼綅鏁扮敱
shift[2:0]
鍐冲畾
浠ｇ爜锛?/p>
module Verilog1(inp,outp,shift);
input [7:0] inp;
input [2:0] shift;
output reg [7:0] outp;
always
begin
outp=inp<<shift;
end
endmodule