1
FPGA
鍣ㄤ欢鏈変笁绫婚厤缃笅杞芥柟寮忥細涓诲姩閰嶇疆鏂瑰紡锛?/p>
AS
锛夊拰琚姩閰嶇疆鏂瑰紡锛?/p>
PS
锛?/p>
鍜屾渶甯哥敤鐨?/p>
(JTAG)
閰嶇疆鏂瑰紡銆?/p>
涓诲姩涓茶锛?/p>
AS
锛?/p>
鐢?/p>
FPGA
鍣ㄤ欢寮曞閰嶇疆鎿嶄綔杩囩▼锛屽畠鎺у埗鐫�澶栭儴瀛樺偍鍣ㄥ拰鍒濆鍖栬繃绋嬶紝
EPCS
绯诲垪
.
濡?/p>
EPCS1,EPCS4
閰嶇疆鍣ㄤ欢涓撲緵
AS
妯″紡锛?/p>
鐩墠鍙敮鎸?/p>
Stratix II
鍜?/p>
Cyclone
绯诲垪
銆?/p>
浣跨敤
Altera
涓茶閰嶇疆鍣ㄤ欢鏉ュ畬鎴愩�?/p>
Cyclone
鍣ㄤ欢澶勪簬涓诲姩鍦颁綅锛岄厤缃櫒浠跺浜庝粠灞炲湴浣嶃�傞厤缃暟鎹�?/p>
杩?/p>
DATA0
寮曡剼閫佸叆
FPGA
銆傞厤缃暟鎹鍚屾鍦?/p>
DCLK
杈撳叆涓婏紝
1
涓椂閽熷懆鏈熶紶閫?/p>
1
浣嶆暟鎹�?/p>
AS
閰嶇疆鍣ㄤ欢鏄竴绉嶉潪鏄撳け鎬с�佸熀浜?/p>
flash
瀛樺偍鍣ㄧ殑瀛樺偍鍣紝鐢ㄦ埛鍙互浣跨敤
altera
鐨?/p>
ByteBlaster II
鍔犺浇鐢电紗銆?/p>
altera
鐨勨�渁ltera programming unit鈥濇垨鑰呯涓夋柟鐨勭紪绋嬪櫒鏉?/p>
瀵归厤缃姱鐗囪繘琛岀紪绋嬨�傚畠涓?/p>
FPGA
鐨勬帴鍙ｄ负浠ヤ笅绠�鍗曠殑
4
涓俊鍙风嚎锛?/p>
.
涓茶鏃堕挓杈撳叆
锛?/p>
DCLK
锛?/p>
锛?/p>
鏄湪閰嶇疆妯″紡涓?/p>
FPGA
鍐呴儴鐨勬尟鑽″櫒
锛?/p>
oscillator
锛?/p>
浜х敓鐨勶紝
鍦ㄩ厤缃畬鎴愬悗锛岃鎸崱鍣ㄥ皢琚叧鎺夈�傚伐浣滄椂閽熷湪
20MHz
宸﹀彸锛岃�?/p>
fast AS
鏂瑰紡涓嬶紙
stratix
II
鍜?/p>
cyclone
II
鏀寔璇ョ閰嶇疆鏂瑰紡锛?/p>
锛?/p>
DCLK
鏃堕挓宸ヤ綔鍦?/p>
40MHz
宸﹀彸锛屽湪
altera
鐨勪富鍔ㄤ覆
琛岄厤缃姱鐗囦腑锛?/p>
鍙湁
EPCS16
鍜?/p>
EPCS64
鐨?/p>
DCLK
鍙互鏀寔鍒?/p>
40MHz
锛?/p>
EPCS1
鍜?/p>
EPCS4
鍙?/p>
鑳芥敮鎸?/p>
20MHz
銆?/p>
.
AS
鎺у埗淇″彿杈撳叆锛?/p>
ASDI
锛?/p>
.
鐗囬�変俊鍙凤紙
nCS
锛?/p>
锛?/p>
.
涓茶鏁版嵁杈撳嚭锛?/p>
DATA
锛?/p>
銆?/p>