6.6
鐜板満鍙紪绋嬮樀鍒?/p>
鐜板満鍙紪绋嬮棬闃靛垪
(Field Programmable Gate Array
锛?/p>
FPGA)
鏄?/p>
80
骞翠唬涓悗鏈熷彂灞曡捣鏉?/p>
鐨勪竴绉嶅彲缂栫▼鐨勫ぇ瑙勬ā闆嗘垚鍣ㄤ欢銆傚畠鏄敱鎺╄啘鍙紪绋嬮棬闃靛垪鍜屽彲缂栫▼閫昏緫鍣ㄤ欢婕斿彉鑰屾潵鐨勶紝
灏嗗畠浠殑鐗规�х粨鍚堝湪涓�璧凤紝浣?/p>
FPGA
鏃㈡湁闂ㄩ樀鍒楃殑楂橀�昏緫瀵嗗害鍜岄�氱敤鎬э紝鍙堟湁鍙紪绋嬮�昏緫鍣?/p>
浠剁殑鐢ㄦ埛鍙紪绋嬬壒鎬с�傞�氬父鐢卞竷绾胯祫婧愬洿缁曠殑鍙紪绋嬪崟鍏?/p>
(
鎴栧畯鍗曞厓
)
鏋勬垚闃靛垪锛屽啀鐢卞彲缂栫▼
I
锛?/p>
O
鍗曞厓鍥寸粫闃靛垪鏋勬垚锛岀敤鎴峰彲浠ラ�氳繃缂栫▼灏嗚繖浜涙ā鍧楄繛鎺ユ垚鎵�闇�瑕佺殑鏁板瓧绯荤粺
銆?/p>
Xilinx
鍏徃鑷?/p>
1985
鎺ㄥ嚭绗竴鐗?/p>
FPGA
浠ユ潵锛屽凡闄嗙画鎺ㄥ嚭浜?/p>
XC2000
锛?/p>
XC3000
锛?/p>
XC3100
锛?/p>
XC4000
锛?/p>
XC5200
鍜?/p>
XC8000
绛?/p>
FPGA
绯诲垪浜у搧銆傚叾鍔熻兘鍜屽師鐞嗗熀鏈浉鍚岋紟浣嗗悗闈㈠嚑绉嶅櫒浠跺湪
缁撴瀯銆佽妯″拰鎬ц兘涓婃湁鎵�鏀硅繘銆備互
XC2000
绯诲垪涓轰緥锛屼粙缁?/p>
FPGA
鐨勭粨鏋勫拰缂栫▼閰嶇疆鍘熺悊鍙婂簲
鐢ㄣ�?/p>
6.6.1 FPGA
鐨勫熀鏈粨鏋?/p>
FPGA
涓昏鐢变笁绉嶅彲缂栫▼閫昏緫鍗曞厓鍜屼竴涓敤浜庡瓨鏀剧紪绋嬫暟鎹殑闈欐�佸瓨鍌ㄥ櫒
(SRAM)
缁勬垚銆?/p>
涓夌鍙紪绋嬮�昏緫鍗曞厓鏄彲缂栫▼閫昏緫鍧?/p>
(Configurable Logic Block
锛?/p>
CLB)
銆佸彲缂栫▼杈撳叆锛忚緭
鍑哄潡
(Input
锛?/p>
Output Block
锛?/p>
IOB)
鍜屽彲缂栫▼鍐呴儴浜掕繛
(Programmable Interconnet ,PI)
锛岃繖
涓夌鍙紪绋嬮�昏緫鍗曞厓鐨勯厤缃�佸伐浣滅姸鎬侀兘鐢遍潤鎬佸瓨鍌ㄥ櫒涓殑鏁版嵁鍐冲畾銆?/p>
FPGA
鐨勫熀鏈粨鏋勭ず
鎰忓浘濡傚浘
6-6-l
鎵�绀恒�?/p>
1
锛庡彲缂栫▼閫昏緫鍧?/p>
(CLB)
CLB
鏄?/p>
FPGA
鐨勫熀鏈�昏緫鍗曞厓锛涘湪
FPGA
鍐呮帓鍒楁垚鏂归樀锛屾瘡涓?/p>
CLB
閫氳繃閰嶇疆鍙垚涓哄叿澶囦竴
瀹氶�昏緫鍔熻兘鐨勫皬鍗曞厓锛?/p>
CLB
涔嬮棿閫氳繃浜掕繛鍙互瀹炵幇鐢ㄦ埛鎸囧畾鐨勫鏉傜殑閫昏緫鍔熻兘銆?/p>
XC2000
绯诲垪
涓殑
XC2064
鏈?/p>
64
涓?/p>
CLB
锛屾帓鍒楁垚
8
脳
8
鐨勭煩闃碉紝
XC2018
涓湁
100
涓?/p>
CLB
鎺掑垪鎴?/p>
10
脳
10
鐨勭煩
闃点�?/p>
XC2000
绯诲垪
CLB
缁撴瀯绀烘剰鍥惧鍥?/p>
6-6-2
鎵�绀恒�?/p>