榫欐簮鏈熷垔缃?/p>
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鍩轰簬
FPGA
鐨勫姞鍑忚鏃跺櫒璁捐
浣滆�咃細闄堥緳闄?/p>
鏉ユ簮锛氥�婄數瀛愭妧鏈笌杞欢宸ョ▼銆?/p>
2015
骞寸
11
鏈?/p>
鎽?/p>
瑕?/p>
鍩轰簬鐜板満鍙紪绋嬮棬闃靛垪
FPGA
锛堢郴
Field Programmable Gate Array
鐨勭缉鍐欙級鐨勭數璺郴
缁熻璁★紝鏄洰鍓嶆暟瀛楃數璺璁＄殑涓绘祦鏂规硶涔嬩竴銆傛湰鏂囬槓杩颁簡鍩轰簬
FPGA
鐨勫姞鍑忚鏃跺櫒璁捐鏂?/p>
娉曪紝鎻愬嚭浜嗙郴缁熺數璺殑璁捐鎬濊矾鍙婂悎鐞嗘柟妗堬紝璇ヨ璁¤鏃跺櫒鍏煎绉掑姞璁℃椂鍜岀鍑忓�掕鏃剁殑鍔?/p>
鑳姐�傚苟鍊熷姪浜?/p>
Quartus II
寮�鍙戝钩鍙板畬鎴愪豢鐪熻璁★紝閫氳繃
FPGA
纭欢瀹為獙绠辫繘琛屾祴璇曪紝楠岃瘉缁撴灉
琛ㄦ槑鏈枃鎻愬嚭鐨勮璁℃柟妗堟纭彲琛屻�?/p>
銆愬叧閿瘝銆?/p>
FPGA Quartus II EDA
璁℃暟鍣?/p>
闅忕潃鍏ㄧ悆缁忔祹鐨勯珮閫熷彂灞曘�佺瀛︽妧鏈殑涓嶆柇鍒涙柊锛岀數瀛愯璁¤嚜鍔ㄥ寲
EDA
锛堢郴
Electronic
Design Automation
鐨勭缉鍐欙級鎶�鏈紝鍦ㄧ數瀛愪俊鎭伐绋嬮鍩熸垚涓轰簡褰撲粖涓栫晫涓婃渶鍏堣繘鐨勭數瀛愮數璺
璁℃妧鏈�傚畠渚濋潬鍔熻兘寮哄ぇ鐨勭數瀛愯绠楁満锛屽湪
EDA
宸ュ叿杞欢骞冲彴涓婏紝瀵逛互纭欢鎻忚堪璇█
HDL
锛堢郴
Hardware Description Language
鐨勭缉鍐欙級涓虹郴缁熼�昏緫鎻忚堪鎵嬫瀹屾垚鐨勮璁℃枃浠讹紝鑷姩鍦板畬
鎴愰�昏緫缂栬瘧銆佸寲绠�銆佸垎鍓层�佺患鍚堛�佷紭鍖栥�佷豢鐪燂紝鐩磋嚦涓嬭浇鍒板彲缂栫▼閫昏緫鍣ㄤ欢濡傜幇鍦哄彲缂栫▼闂ㄩ樀
鍒?/p>
FPGA
鎴栧鏉傜殑鍙紪绋嬮�昏緫鍣ㄤ欢
CPLD
锛堢郴
Complex Programmable Logic Device
鐨勭缉鍐欙級鎴?/p>
涓撶敤闆嗘垚鐢佃矾
ASIC
锛堢郴
Application Specific Integrated Circuit
鐨勭缉鍐欙級鑺墖涓紝浠庤�屽疄鐜版棦瀹?/p>
鐢靛瓙鐢佃矾鐨勫姛鑳界郴缁熻璁°�傚洜姝わ紝鍦ㄧ數瀛愬伐绋嬪簲鐢ㄩ鍩燂紝鐢?/p>
EDA
鎶�鏈潵瀹屾垚鐢靛瓙绯荤粺鐨勮
璁★紝宸叉垚涓虹幇浠ｇ數瀛愯璁℃妧鏈殑鏍稿績銆?/p>
1
璁捐鏂规
鏈枃鎻愬嚭鐨勭郴缁熻璁℃柟妗堥噰鐢ㄨ嚜椤跺悜涓嬬殑璁捐鏂规硶锛屼粠绯荤粺璁捐鍏ユ墜锛屽湪椤跺眰瀵硅鏃跺櫒鏁?/p>
浣撶數璺郴缁熻繘琛屽姛鑳芥柟妗嗗浘鐨勫垝鍒嗗拰缁撴瀯璁捐锛屽湪鏂规鍥句竴绾ц繘琛屼豢鐪熴�佺籂閿欙紝鐢ㄧ‖浠舵弿杩拌
瑷�锛?/p>
HDL
锛夊楂樺眰娆＄殑绯荤粺琛屼负杩涜鎻忚堪骞朵簬鍔熻兘涓�绾ц繘琛岄獙璇侊紱绯荤粺鐢佃矾鐨勮璁′緷鎵樹簬
FPGA
纭欢骞冲彴锛岄噰鐢ㄨ秴楂橀�熼泦鎴愮數璺‖浠舵弿杩拌瑷�
鈥?/p>
VHDL
锛堢郴
Very High Speed Integrated
Circuit Hardware Description Language
鐨勭缉鍐欙級锛岃璁″湪
Quartus II
寮�鍙戠幆澧冧笅杩涜锛涜璁″嚭鐨?/p>
璁℃椂鍣ㄨ鏃惰寖鍥翠负
00.00--59.00
绉掞紝绮惧害涓?/p>
0.01
绉掞紝鍏锋湁绉掑姞鍜岀鍑忚鏃躲�佹竻闆躲�佽鏃?/p>
鈥?/p>
鍋滄
鈥?/p>
缁х画璁℃椂绛夊姛鑳斤紝瀵圭櫨鍒嗕箣绉掑拰绉掔殑璁℃暟淇℃伅閲囩敤鍥涗綅
LED
鏁扮爜绠¤繘琛屽弸濂界晫闈㈡樉绀恒�傜郴
缁熻璁℃鍥惧鍥?/p>
1
鎵�绀恒�?/p>
2
鏍稿績妯″潡璁捐
2.1
杈撳叆閰嶇疆妯″潡璁捐
渚濇嵁鍔犲噺璁℃椂鍣ㄨ璁＄郴缁熸鍥惧浘
1
鎵�绀猴紝杈撳叆閰嶇疆妯″潡鍖呮嫭鍙嶅悜鍣ㄩ�昏緫闂ㄣ�佷笌閫昏緫闂ㄤ袱閮?/p>
鍒嗐�傚熀浜庤璁″姛鑳介渶姹傦紝鍙嶅悜鍣ㄩ�昏緫闂ㄣ�佷笌閫昏緫闂ㄧ殑
VHDL
鎻忚堪璁捐濡傚浘
2
鎵�绀恒�?/p>