绗?/p>
3
绔?/p>
VHDL
鍩虹
3-1
锛氱敾鍑轰笌涓嬩緥瀹炰綋鎻忚堪瀵瑰簲鐨勫師鐞嗗浘绗﹀彿鍏冧欢锛?/p>
ENTITY buf3s IS --
瀹炰綋
1
锛氫笁鎬佺紦鍐插櫒
PORT (input : IN STD_LOGIC ; --
杈撳叆绔?/p>
enable : IN STD_LOGIC ; --
浣胯兘绔?/p>
output : OUT STD_LOGIC ) ; --
杈撳嚭绔?/p>
END buf3x ;
ENTITY mux21 IS --
瀹炰綋
2
锛?/p>
2
閫?/p>
1
澶氳矾閫夋嫨鍣?/p>
PORT (in0, in1, sel : IN STD_LOGIC;
output : OUT STD_LOGIC);
3-1.
绛旀
3-2.
鍥?/p>
3-30
鎵�绀虹殑鏄?/p>
4
閫?/p>
1
澶氳矾閫夋嫨鍣紝
璇曞垎鍒敤
IF_THEN
璇彞鍜?/p>
CASE
璇?/p>
鍙ョ殑琛ㄨ揪鏂瑰紡鍐欏嚭姝ょ數璺殑
VHDL
绋嬪簭銆?/p>
閫夋嫨鎺у埗鐨勪俊鍙?/p>
s1
鍜?/p>
s0
鐨勬暟鎹被鍨嬩负
STD_LOGIC_VECTOR
锛?/p>
褰?/p>
s1='0'
锛?/p>
s0='0'
锛?/p>
s1='0'
锛?/p>
s0='1'
锛?/p>
s1='1'
锛?/p>
s0='0'
鍜?/p>
s1='1'
锛?/p>
s0='1'
鍒嗗埆鎵ц
y<=a
銆?/p>
y<=b
銆?/p>
y<=c
銆?/p>
y<=d
銆?/p>
3-2.
绛旀
LIBRARY IEEE;
USE MUX41 IS
PORT(s:IN STD_LOGIC_VECTOR(1 DOWNTO 0); --
杈撳叆閫夋嫨淇″彿
a,b,c,d:IN STD_LOGIC; --
杈撳叆淇″彿
y:OUT STD_LOGIC);--
杈撳嚭绔?/p>
END ENTITY;
ARCHITECTURE ART OF MUX41 IS
BEGIN
PROCESS(s)
BEGIN
IF (S="00") THEN y<=a;
ELSIF (S="01") TH EN y<=b;
ELSIF (S="10") TH EN y<=c;
ELSIF (S="11") TH EN y<=d;
ELSE y<=NULL;
END IF;
EDN PROCESS;
END ART;
LIBRARY IEEE;
USE MUX41 IS
PORT(s:IN STD_LOGIC_VECTOR(1 DOWNTO 0); --
杈撳叆閫夋嫨淇″彿
a,b,c,d:IN STD_LOGIC; --
杈撳叆淇″彿
y:OUT STD_LOGIC);--
杈撳嚭绔?/p>
END MUX41;
ARCHITECTURE ART OF MUX41 IS
BEGIN