1
锛庢ā鍧楃殑鍩烘湰缁勬垚閮ㄥ垎鏈夊摢浜涳紵鍝嚑涓儴鍒嗗繀椤诲嚭鐜帮紵
绛旓細
妯″潡鐨勫熀鏈粍鎴愰儴鍒嗗寘鎷細
鍏抽敭瀛?/p>
module
锛?/p>
妯″潡鍚嶃�?/p>
绔彛鍒楄〃銆?/p>
绔彛澹版槑鍜屽彲閫夌殑鍙傛暟澹版槑锛?/p>
妯″潡鍐呴儴杩樻湁
5
涓熀鏈粍鎴愰儴鍒嗘槸锛氬彉閲忓０鏄庛�佹暟鎹祦璇彞銆佷綆灞傛ā鍧楀疄渚嬨�佽涓鸿鍙ュ潡浠ュ強浠?/p>
鍔″拰鍑芥暟銆?/p>
鍦ㄦā鍧楃殑鎵�鏈夌粍鎴愰儴鍒嗕腑锛屽彧鏈?/p>
module
銆佹ā鍧楀悕鍜?/p>
endmodule
蹇呴』鍑虹幇锛屽叾浠栭儴鍒嗛兘鏄彲閫?/p>
鐨勶紝鐢ㄦ埛鍙互鏍规嵁璁捐鐨勯渶瑕侀殢鎰忛�夌敤銆?/p>
2
锛庝竴涓笉涓庡閮ㄧ幆澧冧氦浜掔殑妯″潡鏄惁鏈夌鍙ｏ紵妯″潡瀹氫箟涓槸鍚︽湁绔彛鍒楄〃锛?/p>
绛旓細
涓ユ牸鎰忎箟涓婅锛屼竴涓ā鍧楀鏋滀笌澶栫晫娌℃湁浠讳綍浜や簰锛岄偅涔堣嚜鐒舵槸涓嶉渶瑕佹湁鑰屼笖鏄笉鍙兘鏈夌
鍙ｇ殑銆傚湪娌℃湁绔彛鐨勬儏鍐典笅锛岀鍙ｅ垪琛ㄨ嚜鐒朵篃鏄笉瀛樺湪鐨勩�?/p>
3
锛庝竴涓?/p>
4
浣嶅苟琛岀Щ浣嶅瘎瀛樺櫒鐨?/p>
I/O
寮曡剼濡備笅鍥炬墍绀恒�傚啓鍑烘ā鍧?/p>
shift_reg
鐨勫畾涔夛紝鍙渶鍐欏嚭绔彛
鍒楄〃鍜岀鍙ｅ畾涔夛紝涓嶅繀鍐欏嚭妯″潡鐨勫唴閮ㄧ粨鏋勩�?/p>
绛旓細
妯″潡浠ｇ爜濡備笅锛?/p>
module shift_reg(clock,reg_in,reg_out);
input clock;
input [3:0] reg_in;
output [3:0] reg_out;
//********XXXXXXX**************
endmodule
4
锛庡畾涔変竴涓《灞傛ā鍧?/p>
stimulus
锛屽湪鍏朵腑澹版槑
reg
鍙橀噺
REG_IN
锛?/p>
4
浣嶏級鍜?/p>
CLK
锛?/p>
1
浣嶏級浠ュ強
wire
鍙橀噺
REG_OUT
锛?/p>
4
浣嶏級
銆傚湪鍏朵腑璋冪敤锛堝疄渚嬪紩鐢級妯″潡
shift_reg
锛屽疄渚嬪悕涓?/p>
sr1
锛屼娇鐢ㄩ『搴忕
鍙ｈ繛鎺ャ�?/p>
绛旓細
妯″潡浠ｇ爜濡備笅
module stimulus();
reg CLOCK;
reg [3:0] REG_IN;
wire [3:0] REG_OUT;
//*******connect in order************
shift_reg sr1(CLOCK,REG_IN,REG_OUT);
endmodule
绉讳綅
瀵勫瓨鍣?/p>
shift_reg
锛?/p>
4
浣嶏級
reg_in [3:0]
clock
reg_out [3:0]