璁?/p>
Verilog
浠跨湡鐘舵�佹満鏃跺彲浠ユ樉绀虹姸鎬佸悕
Situation:
鎴戜滑骞虫椂浣跨敤
Verilog
杩涜鐘舵�佹満缂栫爜鏃讹紝閫氬父浣跨敤
parameter
瀵圭姸鎬佸悕杩涜瀹氫箟锛岃繖鏍峰啓
Case
璇彞鐨勬椂鍊欏氨涓嶄細瀵硅繖涓�涓?/p>
10
鎽镐笉鐫�澶磋剳銆?/p>
鍙槸閫氬父杩欐牱鍋氱殑璇濓紝鍦?/p>
Modelsim
閲岀湅鍒扮殑杩樻槸涓�涓?/p>
10
锛屼娇鎺掗敊闈炲父鍥伴毦锛?/p>
鐗瑰埆鏄湪鐢?/p>
OneHot
缂栫爜鐨勬椂鍊欙紝灏辩湅鍒颁竴涓?/p>
0
涓棿鐨勪竴涓?/p>
1 #_#
绠�鐩磋鐤帀銆?/p>
Question:
鎴戜滑鍙笉鍙互鍍?/p>
VHDL
涓�鏍凤紝鍦ㄤ豢鐪熺殑鏃跺�欑湅鍒扮姸鎬佸悕瀛楋紝鑰屼笉浠?/p>
浠呮槸鐘舵�佺紪鐮佸憿锛熺瓟妗堝綋鐒舵槸鍙互鐨勬媺锛屼簨鍦ㄤ汉涓哄槢锛?/p>
Solution1:
鍙﹀瀹氫箟涓�涓?/p>
reg:
state_name
锛岄暱搴︽牴鎹姸鎬佸悕绉伴暱搴﹁�屾敼鍙橈紙鐘舵�佸悕绉板瓧绗︽暟
x8
锛夛紱鍦ㄦ瘡涓?/p>
鐘舵�佹墽琛岀殑璇彞涓姞鍏?/p>
state_name
=
鈥業DLE鈥?
绫讳技鐨勪竴鍙ヨ鍙ワ紱浠跨湡鏃舵坊鍔?/p>
state_name
杩涜瑙傚療锛屼娇鐢?/p>
ASCII
Radix
銆?/p>
Solution2:
浣跨敤濡備笅璇彞锛氫唬鐮?/p>
:`ifdef
SIMULATION
parameter
S_idle
=
鈥榠dle鈥?
parameter
S_decode
=
鈥榙ecode鈥?
parameter
S_start
=
鈥榮tart
鈥?
parameter
S_wait
=
鈥榳ait鈥?
parameter
state_wid_msb
=
47;
`else
parameter
S_idle
=
4鈥檅0001;
parameter
S_decode
=
4鈥檅0010;
parameter
S_start
=
4鈥檅0100;
parameter
S_wait
=
4鈥檅1000;
parameter
state_wid_msb
=
3;
`endif
reg
[state_wid_msb:0] state;
鍙鍦ㄤ豢鐪熺殑鏃跺�?/p>
`define SIMULATION
灏卞彲浠ヤ簡銆備竴鏍?/p>
鐢?/p>
ASCII Radix
鏌ョ湅銆?/p>
tips:
鎰熻阿澶у鐨勯槄璇伙紝鏈枃鐢辨垜鍙告敹闆嗘暣缂栥�備粎渚涘弬闃咃紒