榫欐簮鏈熷垔缃?/p>
http://www.qikan.com.cn
鍩轰簬
FPGA
鐨勮棰戝浘鍍忛噰闆嗙郴缁熺殑璁捐涓?/p>
瀹炵幇
浣滆�咃細浣曠ⅶ璐?/p>
鏉ユ簮锛氥�婁环鍊煎伐绋嬨�?/p>
2012
骞寸
28
鏈?/p>
鎽樿锛?/p>
閽堝瑙嗛鍥惧儚閲囬泦瀵瑰彲闈犳�у拰瀹炴椂鎬х殑瑕佹眰锛屾彁鍑哄苟瀹炵幇浜嗕竴绉嶄互
FPGA
涓烘帶鍒?/p>
鐨勮棰戝浘褰㈤噰闆嗙郴缁熴�傞噰鐢?/p>
Altera
鍏徃鐢熶骇鐨?/p>
Cyclone
鈪?/p>
EP2C35F672C6
鑺墖锛岃礋璐ｆ帴鍙楀拰澶?/p>
鐞嗘潵鑷?/p>
ADV7181
瑙ｇ爜鍚庣殑瑙嗛鏁版嵁锛屽皢璇ユ暟鎹浆鎹㈠埌
RGB
鑹插煙鍚庤緭鍑哄埌
ADV7123
鑺墖銆傞�?/p>
杩囩浉鍏崇殑璋冭瘯锛岀郴缁熼�氱敤鎬уソ锛岀Щ鍔ㄦ�ф瘮杈冨ソ銆?/p>
Abstract
锛?/p>
For the demand of reliability and real
鈥?/p>
time characteristics for video collection
锛?/p>
this
paper proposes a video collection system based on FPGA. The system which adopts Cyclone II series
EP2C35F672C6 image processing chip as its core
锛?/p>
it receives and deals with the video data from the
ADV7123. According to some experiment
锛?/p>
the common usage and mobility of system is fine.
鍏抽敭璇嶏細
FPGA
锛?/p>
ADV7181
锛?/p>
RGB
鑹插煙锛?/p>
ADV7123
鑺墖
Key words
锛?/p>
FPGA
锛?/p>
ADV7181
锛?/p>
RGB color
锛?/p>
ADV7123 chip
涓浘鍒嗙被鍙凤細
TP39
鏂囩尞鏍囪瘑鐮侊細
A
鏂囩珷缂栧彿锛?/p>
1006
鈥?/p>
4311
锛?/p>
2012
锛?/p>
28
鈥?/p>
0200
鈥?/p>
02
0
寮曡█
闅忕潃鏁板瓧鍜屽濯掍綋鎶�鏈殑涓嶆柇鍙戝睍鍜岃繘姝ワ紝鏁板瓧鍥惧儚锛堝挨鍏舵槸瑙嗛鍥惧儚锛夊鐞嗘妧鏈搴旂敤
浜庡绉嶉鍩熶腑
[1]
銆傝�?/p>
FPGA
鍏锋湁寰堝己鐨勭伒娲绘�э紝浣庡紑鏀炬垚鏈紝鍙互閫氳繃杞欢锛屾牴鎹渶瑕佹棤闄愭鐨勬洿鏀瑰叾鍐呴儴纭欢閫?/p>
杈戯紝閲囩敤鍩轰簬闂ㄧ數璺殑纭欢绠楁硶锛岃繍绠楅�熷害鎺ヨ繎浜庝笓鐢ㄩ泦鎴愯姱鐗囷紝鑳藉婊¤冻瀹炴椂鍥惧儚澶勭悊鐨勮
姹?/p>
[2]
銆傚洜姝ゆ湰鏂囨墍鐮旂┒鍜屽疄鐜扮殑姝ｆ槸涓�绉嶅熀浜?/p>
FPGA
鐨勪綆鎴愭湰鍥惧儚閲囬泦澶勭悊绯荤粺銆?/p>
1
瑙嗛鍥惧儚閲囬泦绯荤粺鐨勭‖浠惰璁?/p>
濡傚浘
1
鎵�绀猴紝璇ョ郴缁熷寘鎷嚑涓姛鑳芥ā鍧楋細鍥惧儚閲囬泦妯″潡銆佸浘鍍忓鐞嗘ā鍧椼�佸浘鍍忔樉绀烘ā鍧椼�?/p>
鍏朵腑鍥惧儚閲囬泦妯″潡涓昏鐢卞鎺ユ憚鍍忓ご鍜?/p>
ADV7181
瑙ｇ爜鑺墖缁勬垚锛屽畬鎴愯棰戜俊鍙风殑閲囬泦鍜岀‖浠?/p>
瑙ｇ爜鍔熻兘锛屽苟浠?/p>
ITU
鈥?/p>
656
鏍囧噯杈撳嚭
YUV 4
锛?/p>
2
锛?/p>
2
淇″彿锛涘浘鍍忓鐞嗘ā鍧楅�夌敤鐨?/p>
FPGA
鏄?/p>
Altera
鍏徃鐢熶骇鐨?/p>
Cyclone
鈪?/p>
EP2C35F672C6
鑺墖
[3
锛?/p>
4]
鏋勬垚锛屽畬鎴愮郴缁熸帶鍒讹紝瑙嗛淇″彿鐨勯噰闆嗕互鍙?/p>
鍚庣画澶勭悊绛夊伐浣滐紱鍥惧儚鏄剧ず妯″潡涓昏鐢?/p>
ADV7123
鑺墖銆?/p>
VGA
鎺ュ彛鍜?/p>
CRT
鏄剧ず鍣ㄧ瓑缁勬垚锛屼富
瑕佸畬鎴愯棰戜俊鍙风殑鏁版ā杞崲锛岃緭鍑哄苟鏄剧ず瑙嗛淇″彿銆?/p>