瀹為獙涓?/p>
妯?/p>
-5
璁℃暟鍣ㄧ殑璁捐涓庡疄鐜?/p>
涓�锛庡疄楠岀洰鐨?/p>
1
锛庝娇鐢?/p>
ISE
杞欢璁捐骞朵豢鐪燂紱
2
锛庡浼氱▼搴忎笅杞姐�?/p>
浜岋紟瀹為獙鍐呭
浣跨敤
ISE
杞欢杩涜妯?/p>
-5
璁℃暟鍣ㄧ殑璁捐涓庡疄鐜般�?/p>
涓夛紟瀹為獙姝ラ
1.
缂栧啓鏂囨湰鏂囦欢骞剁紪璇?/p>
2.
杞欢浠跨湡
3.
杩涜纭欢閰嶇疆
鍥涳紟瀹為獙鍘熺悊
1. ISE
杞欢鏄竴涓敮鎸佹暟瀛楃郴缁熻璁＄殑寮�鍙戝钩鍙般�?/p>
2.
鐢?/p>
ISE
杞欢杩涜璁捐寮�鍙戞椂鍩轰簬鐩稿簲鍣ㄤ欢鍨嬪彿鐨勩�?/p>
娉ㄦ剰锛氳蒋浠惰璁℃椂閫夋嫨
鐨勫櫒浠跺瀷鍙锋槸涓庡疄闄呬笅杞芥澘涓婄殑鍣ㄤ欢鍨嬪彿鐩稿悓銆?/p>
3.
妯?/p>
-5
璁℃暟鍣ㄥ氨鏄粠
0
鍒?/p>
4
閲嶅璁℃暟銆?/p>
涔熷氨鏄锛?/p>
瀹冧竴鍏辫缁忓巻
5
涓姸鎬侊紝
杈撳嚭浠?/p>
000
鍙樺埌
100
鐒跺悗鍐嶅洖鍒?/p>
000
銆傛湰瀹為獙涓敤
Verilog
璇彞鏉ユ弿杩般�?/p>
锛?/p>
1
锛?/p>
鏂板缓宸ョ▼
鍙屽嚮妗岄潰涓娾�?/p>
ISE Design Suite 14.7
鈥濆浘鏍囷紝鍚姩
ISE
杞欢
(
涔熷彲浠庡紑濮嬭彍
鍗曞惎鍔?/p>
)
銆?/p>
姣忔鎵撳紑
ISE
閮戒細榛樿鎭㈠鍒版渶杩戜娇鐢ㄨ繃鐨勫伐绋嬬晫闈€�?/p>
褰撶涓�娆′娇鐢ㄦ椂锛?/p>
鐢变簬杩樻病鏈夊巻鍙插伐绋嬭褰曪紝鎵�浠ュ伐绋嬬鐞嗗尯鏄剧ず绌虹櫧銆傞�夋嫨
File New--Project
閫夐」锛屽湪寮瑰嚭鐨勫璇濇涓緭鍏ュ伐绋嬪悕绉板苟鎸囧畾宸ョ▼璺緞銆?/p>
鐐瑰嚮
Next
鎸夐挳杩涘叆涓嬩竴椤碉紝
閫夋嫨鎵�浣跨敤鐨勮姱鐗囧強缁煎悎銆?/p>
浠跨湡宸ュ叿銆?/p>
璁＄畻鏈轰笂
瀹夎鐨勬墍鏈夌敤浜庝豢鐪熷拰缁煎悎鐨勭涓夋柟
EDA
宸ュ叿閮藉彲浠ュ湪涓嬫媺鑿滃崟涓壘鍒般�傚湪鍥句腑
鎴戜滑閫夌敤浜?/p>
Spartan6 XC6SLX16
鑺墖锛岄噰鐢?/p>
CSG324
灏佽锛岃繖鏄?/p>
NEXYS3
寮�鍙戞澘鎵�鐢?/p>
鐨勮姱鐗囥�傚彟澶栵紝鎴戜滑閫夋嫨
Verilog
浣滀负榛樿鐨勭‖浠舵弿杩拌瑷�銆?/p>
鍐嶇偣鍑?/p>
Next
鎸夐挳杩涘叆涓嬩竴椤碉紝
杩欓噷鏄剧ず浜嗘柊寤哄伐绋嬬殑淇℃伅锛?/p>
纭鏃犺鍚庯紝
鐐?/p>
鍑?/p>
Finish
灏卞彲浠ュ缓绔嬩竴涓畬鏁寸殑宸ョ▼浜嗐�?/p>
锛?/p>
2
锛?/p>
璁捐杈撳叆鍜屼唬鐮佷豢鐪?/p>
鍦ㄥ伐绋嬬鐞嗗尯浠绘剰浣嶇疆鍗曞嚮榧犳爣鍙抽敭锛屽湪寮瑰嚭鐨勮彍鍗曚腑閫夋嫨
New Source
鍛?/p>
浠わ紝閫夋嫨
Verilog Module
杈撳叆锛屽苟杈撳叆
Verilog
鏂囦欢鍚嶃�?/p>
鍗曞嚮
Next
鎸夐挳杩涘叆绔彛瀹氫箟瀵硅瘽妗嗐�傚叾涓?/p>
Module Name
鏍忕敤浜庤緭鍏ユā鍧楀悕锛?/p>
杩欓噷鏄?/p>
mod5cnt
锛屼笅闈㈢殑鍒楄〃妗嗙敤浜庣鍙ｇ殑瀹氫箟銆?/p>
Port Name
琛ㄧず绔彛鍚嶇О锛?/p>
Direction
琛ㄧず绔彛鏂瑰悜
(
鍙�夋嫨涓?/p>
input
銆?/p>
output
鎴?/p>
inout)
锛?/p>
MSB
琛ㄧず淇″彿鏈�楂樹綅锛?/p>
LSB
琛ㄧず淇″彿鏈�浣庝綅锛屽浜庡崟淇″彿鐨?/p>
MSB
鍜?/p>
LSB
涓嶇敤濉啓銆傚綋鐒讹紝绔彛瀹氫箟杩欎竴姝?/p>
鎴戜滑涔熷彲浠ョ暐杩囷紝鍦ㄦ簮绋嬪簭涓啀琛屾坊鍔犮�?/p>
瀹氫箟浜嗘ā鍧楃殑绔彛鍚庯紝鍗曞嚮
Next
杩涘叆涓嬩竴姝ワ紝鐐瑰嚮
Finish
瀹屾垚鍒涘缓銆傝繖鏍凤紝
ISE
灏变細鑷姩鍒涘缓涓�涓?/p>
Verilog
妯″潡鐨勬ā鏉匡紝
骞朵笖鍦ㄦ簮浠ｇ爜缂栬緫鍖烘墦寮�銆?/p>
绠�鍗曠殑娉?/p>
閲娿�佹ā鍧楀拰绔彛瀹氫箟宸茬粡鑷姩鐢熸垚锛屾帴涓嬫潵鐨勫伐浣滃氨鏄皢浠ｇ爜缂栧啓瀹屾暣銆?/p>
杈撳叆浠ｇ爜鍚庯紝鎴戜滑杩橀渶瑕佸妯″潡杩涜娴嬭瘯銆傚湪宸ョ▼绠＄悊鍖哄皢
view
璁剧疆涓?/p>
Simulation
锛屽湪浠绘剰浣嶇疆鍗曞嚮榧犳爣鍙抽敭锛屽苟鍦ㄥ脊鍑虹殑鑿滃崟涓�夋嫨
New
Source
锛屽湪
绫诲瀷涓�夋嫨
Verilog
Test
Fixture
锛岃緭鍏ユ祴璇曟枃浠跺悕锛屽崟鍑讳笅涓�姝ャ�傝繖鏃舵墍鏈夊伐
绋嬩腑鐨勬ā鍧楀悕閮戒細鏄剧ず鍑烘潵锛屾垜浠�夋嫨瑕佽繘琛屾祴璇曠殑妯″潡銆傜偣鍑?/p>
Next ,
鍐嶅崟鍑?/p>
Finish
鎸夐挳锛?/p>
ISE
浼氬湪婧愪唬鐮佺紪杈戝尯鑷姩鐢熸垚娴嬭瘯妯″潡鐨勪唬鐮併�傛垜浠湅鍒帮紝
ISE