鏁寸悊浜嗕竴浜?/p>
FPG
鐨勭煡璇嗙偣鍜?/p>
FPGA
鐨勮繘闃惰矾绾?/p>
浠婂ぉ闄嗗缁欏ぇ瀹舵暣鐞嗕簡涓�浜?/p>
FPG
鐨勭煡璇嗙偣鍜?/p>
FPGA
鐨勮繘闃惰矾绾匡紝
灏忔湰鏈噯澶?
濂斤紝瑕佸紑濮嬪垝閲嶇偣鍠姐�?/p>
FPGA
宸ヤ綔鍘熺悊
FPGA
閲囩敤浜嗛�昏緫鍗曞厓闃靛垪
LCA
锛?/p>
Logic Cell Array
锛夎繖鏍蜂竴涓柊姒傚康锛屽唴閮ㄥ寘鎷彲閰嶇疆閫?/p>
杈戞ā鍧?/p>
CLB
锛?/p>
Configurable Logic Block
锛?/p>
銆佽緭鍑鸿緭鍏ユā鍧?/p>
IOB
锛?/p>
Input Output Block
锛夊拰鍐呴儴
杩炵嚎锛?/p>
Interconnect
锛変笁涓儴鍒嗐�?/p>
FPGA
鐨勫熀鏈壒鐐逛富瑕佹湁锛?/p>
1
锛夐噰鐢?/p>
FPGA
璁捐
ASIC
鐢佃矾锛岀敤鎴蜂笉闇�瑕佹姇鐗囩敓浜э紝灏辫兘寰楀埌鍚堢敤鐨勮姱鐗囥�?/p>
2
锛?/p>
FPGA
鍙仛鍏跺畠鍏ㄥ畾鍒舵垨鍗婂畾鍒?/p>
ASIC
鐢佃矾鐨勪腑璇曟牱鐗囥�?/p>
3
锛?/p>
FPGA
鍐呴儴鏈変赴瀵岀殑瑙﹀彂鍣ㄥ拰
I
锛?/p>
O
寮曡剼銆?/p>
4
锛?/p>
FPGA
鏄?/p>
ASIC
鐢佃矾涓璁″懆鏈熸渶鐭�佸紑鍙戣垂鐢ㄦ渶浣庛�侀闄╂渶灏忕殑鍣ㄤ欢涔嬩竴銆?/p>
5) FPGA
閲囩敤楂橀�?/p>
CHMOS
宸ヨ壓锛屽姛鑰椾綆锛屽彲浠ヤ笌
CMOS
銆?/p>
TTL
鐢靛钩鍏煎銆?/p>
鍙互璇达紝
FPGA
鑺墖鏄皬鎵归噺绯荤粺鎻愰珮绯荤粺闆嗘垚搴︺�佸彲闈犳�х殑鏈�浣抽�夋嫨涔嬩竴銆?/p>
FPGA
鏄敱瀛樻斁鍦ㄧ墖鍐?/p>
RAM
涓殑绋嬪簭鏉ヨ缃叾宸ヤ綔鐘舵�佺殑锛屽洜姝わ紝宸ヤ綔鏃堕渶瑕佸鐗囧唴鐨?/p>
RAM
杩涜缂栫▼銆傜敤鎴峰彲浠ユ牴鎹笉鍚岀殑閰嶇疆妯″紡锛岄噰鐢ㄤ笉鍚岀殑缂栫▼鏂瑰紡銆?/p>
鍔犵數鏃讹紝
FPGA
鑺墖灏?/p>
EPROM
涓暟鎹鍏ョ墖鍐呯紪绋?/p>
RAM
涓紝閰嶇疆瀹屾垚鍚庯紝
FPGA
杩涘叆
宸ヤ綔鐘舵�併�傛帀鐢靛悗锛?/p>
FPGA
鎭㈠鎴愮櫧鐗囷紝鍐呴儴閫昏緫鍏崇郴娑堝け锛屽洜姝わ紝
FPGA
鑳藉鍙嶅浣跨敤銆?/p>
FPGA
鐨勭紪绋嬫棤椤讳笓鐢ㄧ殑
FPGA
缂栫▼鍣紝鍙』鐢ㄩ�氱敤鐨?/p>
EPROM
銆?/p>
PROM
缂栫▼鍣ㄥ嵆鍙�?/p>
褰撻渶瑕佷慨鏀?/p>
FPGA
鍔熻兘鏃讹紝鍙渶鎹竴鐗?/p>
EPROM
鍗冲彲銆傝繖鏍凤紝鍚屼竴鐗?/p>
FPGA
锛屼笉鍚岀殑缂栫▼
鏁版嵁锛屽彲浠ヤ骇鐢熶笉鍚岀殑鐢佃矾鍔熻兘銆傚洜姝わ紝
FPGA
鐨勪娇鐢ㄩ潪甯哥伒娲汇�?/p>
FPGA
甯哥敤鏈
1
锛?/p>
LCA(Logic Cell Array)
锛?/p>
閫昏緫鍗曞厓闃靛垪锛?/p>
鍐呴儴鍖呮嫭鍙厤缃�昏緫妯″潡
CLB(Configurable Logic