-
--
1.
浣曡皳
PIE? PIE
鐨勪富瑕佸伐浣滄槸浠�骞?/p>
?
绛旓細
Process Integration
Engineer(
宸ヨ壓鏁村悎宸ョ▼甯?/p>
),
涓昏宸ヤ綔鏄暣
鍚堝悇閮ㄩ棬鐨勮祫婧?/p>
,
瀵瑰伐鑹烘寔缁繘琛屾敼鍠?/p>
,
纭繚浜у搧鐨勮壇鐜囷紙
yield
锛夌ǔ瀹氳壇濂姐�?/p>
2. 200mm
锛?/p>
300mm Wafer
浠ｈ〃浣曟剰涔?/p>
?
绛旓細
8
鍚嬬鐗?/p>
(wafer)
鐩村緞涓?/p>
200mm ,
鐩村緞涓?/p>
300mm
纭呯墖鍗?/p>
12
鍚?/p>
.
3.
鐩墠涓姱鍥介檯鐜版湁鐨勪笁涓伐鍘傞噰鐢ㄥ灏?/p>
mm
鐨勭鐗?/p>
(wafer)
宸ヨ壓锛熸湭鏉ュ寳浜?/p>
鐨?/p>
Fab4(
鍥涘巶
)
閲囩敤澶氬皯
mm
鐨?/p>
wafer
宸ヨ壓锛?/p>
绛旓細褰撳墠
1~3
鍘備负
200mm(8
鑻卞
)
鐨?/p>
wafer,
宸ヨ壓姘村钩宸茶揪
0.13um
宸ヨ壓銆?/p>
鏈潵鍖椾含鍘傚伐鑹?/p>
wafer
灏嗕娇鐢?/p>
300mm(12
鑻卞
)
銆?/p>
4.
鎴戜滑涓轰綍闇�瑕?/p>
300mm?
绛旓細
wafer size
鍙樺ぇ锛屽崟涓�
wafer
涓婄殑鑺墖鏁?/p>
(chip)
鍙樺锛屽崟浣嶆垚鏈?/p>
闄嶄綆
200
鈫?/p>
300
闈㈢Н澧炲姞
2.25
鍊?/p>
,
鑺墖鏁扮洰绾﹀鍔?/p>
2.5
鍊?/p>
5.
鎵�璋撶殑
0.13 um
鐨勫伐鑹鸿兘鍔?/p>
(technology)
浠ｈ〃鐨勬槸浠�骞烘剰涔夛紵
绛旓細鏄寚宸ュ巶鐨勫伐鑹鸿兘鍔涘彲浠ヨ揪鍒?/p>
0.13 um
鐨勬爡鏋佺嚎瀹姐�傚綋鏍呮瀬鐨勭嚎瀹?/p>
鍋氱殑瓒婂皬鏃讹紝鏁翠釜鍣ㄤ欢灏卞彲浠ュ彉鐨勮秺灏忥紝宸ヤ綔閫熷害涔熻秺蹇�?/p>
6.
浠?/p>
0.35um->0.25um->0.18um->0.15um->0.13um
鐨?/p>
technology
鏀瑰彉鍙堜唬琛ㄧ殑鏄?/p>
浠�骞烘剰涔夛紵
绛旓細鏍呮瀬绾跨殑瀹斤紙璇ュ昂瀵哥殑澶у皬浠ｈ〃鍗婂浣撳伐鑹烘按骞崇殑楂樹綆锛?/p>
鍋氱殑瓒婂皬
鏃讹紝宸ヨ壓鐨勯毦搴︿究鐩稿鎻愰珮銆備粠
0.35um -> 0.25um -> 0.18um -> 0.15um ->
0.13um
浠ｈ〃鐫�姣忎竴涓樁娈靛伐鑹鸿兘鍔涚殑鎻愬崌銆?/p>
7.
涓�鑸殑纭呯墖
(wafer)
鍩烘潗
(substrate)
鍙尯鍒嗕负
N,P
涓ょ绫诲瀷锛?/p>
type
锛?/p>
,
浣曡皳
N, P-type
wafer?
绛旓細
N-type wafer
鏄寚鎺烘潅
negative
As)
鐨勭鐗?/p>
, P-type
鐨?/p>
wafer
鏄寚鎺烘潅
positive
B
銆?/p>
In)
鐨勭鐗囥�?/p>
鍏冪礌
(5
浠风數鑽峰厓绱狅紝渚嬪锛?/p>
P
銆?/p>
鍏冪礌
(3
浠风數鑽峰厓绱?/p>
,
渚嬪锛?/p>
8.
宸ュ巶涓鐗囷紙
wafer
锛夌殑鍒堕�犺繃绋嬪彲鍒嗗摢鍑犱釜宸ヨ壓杩囩▼
(module)
锛?/p>
绛旓細涓昏鏈夊洓涓儴鍒嗭細
DIFF
锛堟墿鏁ｏ級銆?/p>
TF(
钖勮啘
)
銆?/p>
PHOTO
锛堝厜鍒伙級銆?/p>
ETCH
锛堝埢铓�锛夈�傚叾涓?/p>
DIFF
鍙堝寘鎷?/p>
FURNACE(
鐐夌
)
銆?/p>
WET(
婀垮埢
)
銆?/p>
IMP(
绂诲瓙
娉?/p>
鍏?/p>
)
銆?/p>
RTP(
蹇�熺儹澶勭悊
)
銆?/p>
TF
鍖呮嫭
PVD(
鐗╃悊姘旂浉娣�绉?/p>
)
銆?/p>
CVD(
鍖栧姘旂浉娣�绉?/p>
)
銆?/p>
CMP(
鍖?
瀛︽満姊扮爺纾?/p>
)
銆傜鐗囩殑鍒堕�犲氨鏄緷鎹鎴风殑瑕佹眰锛屼笉鏂殑鍦ㄤ笉鍚屽伐鑹鸿繃绋?/p>
锛?/p>
module
锛夐棿閲嶅杩涜鐨勭敓浜ц繃绋嬶紝鏈�鍚庡啀鍒╃敤鐢垫�х殑娴嬭瘯锛岀‘淇濅骇鍝佽壇濂姐�?/p>
9.
涓�鑸鐗囩殑鍒堕�犲父浠ュ嚑
P
鍑?/p>
M
鍙婂厜缃╁眰鏁?/p>
(mask layer)
鏉ヤ唬琛ㄧ鐗囧伐鑹虹殑鏃?/p>
闂撮暱鐭紝璇烽棶鍑?/p>
P
鍑?/p>
M
鍙婂厜缃╁眰鏁?/p>
(mask layer)
浠ｈ〃浠�骞烘剰涔夛紵
绛旓細鍑?/p>
P
鍑?/p>
M
浠ｈ〃纭呯墖鐨勫埗閫犳湁鍑犲眰鐨?/p>
Poly(
澶氭櫠纭?/p>
)
鍜屽嚑灞傜殑
metal(
閲?/p>
灞炲绾?/p>
).
涓�鑸?/p>
0.15um
鐨勯�昏緫浜у搧涓?/p>
1P6M( 1
灞傜殑
Poly
鍜?/p>
6
灞傜殑
metal)
銆傝�?/p>
鍏夌僵灞傛暟锛?/p>
mask layer
锛変唬琛ㄧ鐗囩殑鍒堕�犲繀闇�缁忚繃鍑犳鐨?/p>
PHOTO
锛堝厜鍒伙級
.
10. Wafer
涓嬬嚎鐨勭涓�閬撴楠ゆ槸褰㈡垚
start oxide
鍜?/p>
zero layer?
鍏朵腑
start
oxide
鐨勭洰鐨勬槸涓轰綍锛?/p>
绛旓細鈶犱笉甯屾湜鏈夋満鎴愬垎鐨勫厜鍒昏兌鐩存帴纰拌Е
Si
琛ㄩ潰銆?/p>
鈶″湪
laser
鍒诲彿杩囩▼涓?/p>
,
浜﹀彲閬垮厤琚骇鐢熺殑绮夊皹姹℃煋銆?/p>