鏁板瓧绯荤粺璁捐
hdl
璇惧悗绛旀
銆愮瘒涓�锛氭暟瀛楃郴缁熻璁′笌
verilog hdl
銆?/p>
ss=txt>
锛堝涔狅級
eda
锛?/p>
electronic design automation
锛?/p>
灏辨槸浠ヨ绠楁満涓哄伐浣滃钩鍙帮紝浠?/p>
eda
杞欢宸ュ叿涓哄紑鍙戠幆澧冿紝浠?/p>
pld
鍣?/p>
浠舵垨鑰?/p>
asic
涓撶敤闆嗘垚鐢佃矾涓虹洰鏍囧櫒浠惰璁″疄鐜扮數璺郴缁熺殑涓�绉嶆妧鏈�?/p>
1
锛庣數瀛?/p>
cad
锛?/p>
computer aided design
锛?/p>
2
锛庣數瀛?/p>
cae
锛?/p>
computer aided engineering
锛?/p>
3
锛?/p>
eda
锛?/p>
electronic design automation
锛?/p>
eda
鎶�鏈強鍏跺彂灞?/p>
p2
eda
鎶�鏈殑搴旂敤鑼冪暣
1.3
鏁板瓧绯荤粺璁捐鐨勬祦绋?/p>
鍩轰簬
fpga/cpld
鐨勬暟瀛楃郴缁熻璁℃祦绋?/p>
1.
鍘熺悊鍥捐緭鍏?/p>
(schematic diagrams )
2
銆佺‖浠舵弿杩拌瑷�
(hdl
鏂囨湰杈撳叆
)
璁捐杈撳叆
纭欢鎻忚堪璇█涓庤蒋浠剁紪绋嬭瑷�鏈夋湰璐ㄧ殑鍖哄埆
缁煎悎锛?/p>
synthesis
锛?/p>
灏嗚緝楂樺眰娆＄殑璁捐鎻忚堪鑷姩杞寲涓鸿緝浣庡眰娆℃弿杩扮殑杩囩▼
鈼?/p>
琛屼负缁煎悎锛氫粠绠楁硶琛ㄧず銆佽涓烘弿杩拌浆鎹㈠埌瀵勫瓨鍣ㄤ紶杈撶骇锛?/p>
rtl
锛?/p>
鈼?/p>
閫昏緫缁煎悎锛?/p>
rtl
绾ф弿杩拌浆鎹㈠埌閫昏緫闂ㄧ骇锛堝寘鎷Е鍙戝櫒锛?/p>
鈼?/p>
鐗堝浘缁煎悎鎴栫粨鏋勭患鍚堬細浠庨�昏緫闂ㄨ〃绀鸿浆鎹㈠埌鐗堝浘琛ㄧず锛屾垨杞崲鍒?/p>
pld
鍣ㄤ欢鐨勯厤缃綉琛ㄨ〃绀?/p>
缁煎悎鍣ㄦ槸鑳借嚜鍔ㄥ疄鐜颁笂杩拌浆鎹㈢殑杞欢宸ュ叿锛屾槸鑳藉皢鍘熺悊鍥炬垨
hdl
璇?/p>
瑷�鎻忚堪鐨勭數璺姛鑳借浆鍖栦负鍏蜂綋鐢佃矾缃戣〃鐨勫伐鍏?/p>
閫?/p>
閰?/p>
閫傞厤鍣ㄤ篃绉颁负缁撴瀯缁煎悎鍣紝瀹冪殑鍔熻兘鏄皢鐢辩患鍚堝櫒浜х敓鐨勭綉琛ㄦ枃浠?/p>
閰嶇疆浜庢寚瀹氱殑鐩爣鍣ㄤ欢涓紝骞朵骇鐢熸渶缁堢殑鍙笅杞芥枃浠?/p>
瀵?/p>
cpld
鍣ㄤ欢鑰岃█锛屼骇鐢熺啍涓濆浘鏂囦欢锛屽嵆
jedec
鏂囦欢锛涘
fpga
鍣ㄤ欢
鍒欎骇鐢?/p>
bitstream
浣嶆祦鏁版嵁鏂囦欢
p8
浠跨湡锛?/p>
simulation
锛?/p>