3-8译码器的VHDL设计 1.实体框图
2.程序设计
正确的程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY DECODER38A IS
PORT(A2,A1,A0,S1,S2,S3:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY DECODER38A;
ARCHITECTURE ONE OF DECODER38A IS SIGNAL S: STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN
S<=A2&A1&A0&S1&S2&S3; WITH S SELECT
Y<=\ \ \ \ \ \ \
\ \END ARCHITECTURE ONE; 3.仿真波形图
4.仿真波形分析
当S1 S2 S3=100时，只有当A2 A1 A0=111时，Y[7]才输出低电平，否则为高电平，当A2 A1 A0=110时，Y[6]才输出低电平，否则为高电平，当A2 A1 A0=101时，Y[5]才输出低电平，否则为高电平，Y[4]到Y[0]同理。可见该程序设计的是3-8译码器
三、共阳极数码管七段显示译码器的VHDL设计 1.实体框图
2.程序设计
正确的程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY DISPLAY_DECODER IS PORT(A3,A2,A1,A0:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END ENTITY DISPLAY_DECODER;
ARCHITECTURE ONE OF DISPLAY_DECODER IS SIGNAL S: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
S<=A3&A2&A1&A0; WITH S SELECT
Y<=\ \ \ \ \ \ \ \ \ \ \END ARCHITECTURE ONE; 3.仿真波形图