8位数逻辑左移，位数由shift[2:0]决定 代码：
module Verilog1(inp,outp,shift); input [7:0] inp; input [2:0] shift; output reg [7:0] outp;
always
begin
outp=inp< module Verilog1(da,wra_n,clka,clkb,rst_n,wrb,db); input da,wra_n,clka,clkb,rst_n; output reg wrb; output reg [7:0] db; reg [7:0] full=8'b00000000; reg [7:0] out=8'b00000000; always @(posedge clka) begin if(full==8'b11111111) full=8'b00000000; if(wra_n==1'b0) begin case(full) 8'b00000000:begin out[7]=da;full=8'b10000000;end 8'b10000000:begin out[6]=da;full=8'b11000000;end 8'b11000000:begin out[5]=da;full=8'b11100000;end 8'b11100000:begin out[4]=da;full=8'b11110000;end 8'b11110000:begin out[3]=da;full=8'b11111000;end 8'b11111000:begin out[2]=da;full=8'b11111100;end 8'b11111100:begin out[1]=da;full=8'b11111110;end 8'b11111110:begin out[0]=da;full=8'b11111111;end default:full=8'b01010101; endcase end end always @(posedge clkb) begin if(!rst_n) begin wrb=1'b0;db=8'b00000000;end else begin db=8'bxxxxxxxx; if(full==8'b11111111) begin db=out;wrb=1'b1;end else begin wrb=1'b0;db=8'bxxxxxxxx;end end end endmodule